文件列表:

Digital_Clock (0, 2016-10-18)
Digital_Clock\Digital_Clock.cache (0, 2016-10-18)
Digital_Clock\Digital_Clock.cache\wt (0, 2016-10-18)
Digital_Clock\Digital_Clock.cache\wt\java_command_handlers.wdf (401, 2016-10-18)
Digital_Clock\Digital_Clock.cache\wt\synthesis.wdf (3261, 2016-10-18)
Digital_Clock\Digital_Clock.cache\wt\synthesis_details.wdf (97, 2016-10-18)
Digital_Clock\Digital_Clock.cache\wt\webtalk_pa.xml (1512, 2016-10-18)
Digital_Clock\Digital_Clock.cache\wt\xsim.wdf (252, 2016-10-18)
Digital_Clock\Digital_Clock.hw (0, 2016-10-18)
Digital_Clock\Digital_Clock.hw\hw_1 (0, 2016-10-18)
Digital_Clock\Digital_Clock.hw\hw_1\hw.xml (500, 2016-10-18)
Digital_Clock\Digital_Clock.runs (0, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs (0, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_1.xml (443, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_10.xml (485, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_11.xml (497, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_12.xml (497, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_13.xml (497, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_14.xml (497, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_2.xml (443, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_3.xml (269, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_4.xml (485, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_5.xml (248, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_6.xml (265, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_7.xml (485, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_8.xml (485, 2016-10-18)
Digital_Clock\Digital_Clock.runs\.jobs\vrs_config_9.xml (485, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1 (0, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\init_design.pb (5019, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\opt_design.pb (5005, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\place_design.pb (20679, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\route_design.pb (11461, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\runme.log (33667, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\vivado_23468.backup.jou (550, 2016-10-18)
Digital_Clock\Digital_Clock.runs\impl_1\write_bitstream.pb (9968, 2016-10-18)
Digital_Clock\Digital_Clock.runs\synth_1 (0, 2016-10-18)
Digital_Clock\Digital_Clock.runs\synth_1\runme.log (47682, 2016-10-18)
Digital_Clock\Digital_Clock.runs\synth_1\vivado.pb (68644, 2016-10-18)
Digital_Clock\Digital_Clock.sim (0, 2016-10-18)
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Tool and version: Vivado 2014.4 Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq Introduction: This IP is a member of 74LSxx_LIB created by XUP. The 74LSxx_LIB provides the basic IPs having same number and types of gates/functionality that one can find in 74LS IC series. Some of the IP have testbench which can be used to simulated the IP in XSIM. In order to perform the simulation, instantiate the IP in HDL flow and then add the testbech. Setting up the library path: Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where the 74LSxx_LIB directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository. How to use the IP: Step 1: Create a Vivado project Step 2: Set the Project Settings to point to the 74LSxx_LIB path Step 3: Create a block design Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports Step 5: Create a HDL wrapper Step 6: Add constraints file (.xdc) Step 7: Synthesize, implement, and generate the bitstream Step 8: Connect the board, download the bitstream, and verify the design Change log

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