说明：  数据采样时钟/FPGA系统时钟，频率为5MHz,输入的625KHz单频信号,本地OC输出的625KHz单频信号,输出混频滤波后的的1.25Hz单频信号,并对本地oc分频后的显示信号， 然后对混频输出信号分频后的显示信号 。
(Data sampling clock/FPGA system clock, frequency is 5 MHz, input 625 KHz single-frequency signal, local OC output 625 KHz single-frequency signal, output 1.25 Hz single-frequency signal after mixing filtering, and display signal after dividing local OC frequency, and then output signal after dividing the mixing frequency.)