clkdiv26
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：473KB
下载次数：0
上传日期：2019-04-17 14:04:11
上 传 者：
aes1ove
说明： 用VIVADO实现最简单的分频器，分成了三个频率
(Using VIVADO to realize the simplest frequency divider, which is divided into three frequencies)
文件列表:
clkdiv26 (0, 2019-02-13)
clkdiv26\clkdiv26.cache (0, 2019-02-13)
clkdiv26\clkdiv26.cache\wt (0, 2019-02-13)
clkdiv26\clkdiv26.cache\wt\gui_resources.wdf (3692, 2019-02-03)
clkdiv26\clkdiv26.cache\wt\java_command_handlers.wdf (1143, 2019-02-03)
clkdiv26\clkdiv26.cache\wt\project.wpc (121, 2019-02-03)
clkdiv26\clkdiv26.cache\wt\synthesis.wdf (5390, 2019-02-03)
clkdiv26\clkdiv26.cache\wt\synthesis_details.wdf (100, 2019-02-03)
clkdiv26\clkdiv26.cache\wt\webtalk_pa.xml (4202, 2019-02-03)
clkdiv26\clkdiv26.hw (0, 2019-02-13)
clkdiv26\clkdiv26.hw\clkdiv26.lpr (343, 2019-02-03)
clkdiv26\clkdiv26.hw\hw_1 (0, 2019-02-13)
clkdiv26\clkdiv26.hw\hw_1\hw.xml (741, 2019-02-03)
clkdiv26\clkdiv26.hw\hw_1\wave (0, 2019-03-11)
clkdiv26\clkdiv26.ioplanning (0, 2019-02-13)
clkdiv26\clkdiv26.ioplanning\constrs_1 (0, 2019-03-11)
clkdiv26\clkdiv26.ip_user_files (0, 2019-03-11)
clkdiv26\clkdiv26.runs (0, 2019-02-13)
clkdiv26\clkdiv26.runs\.jobs (0, 2019-02-13)
clkdiv26\clkdiv26.runs\.jobs\vrs_config_1.xml (201, 2019-02-03)
clkdiv26\clkdiv26.runs\.jobs\vrs_config_2.xml (215, 2019-02-03)
clkdiv26\clkdiv26.runs\.jobs\vrs_config_3.xml (389, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1 (0, 2019-02-13)
clkdiv26\clkdiv26.runs\impl_1\.Vivado_Implementation.queue.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.Xil (0, 2019-03-11)
clkdiv26\clkdiv26.runs\impl_1\.init_design.begin.rst (189, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.init_design.end.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.opt_design.begin.rst (189, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.opt_design.end.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.place_design.begin.rst (189, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.place_design.end.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.route_design.begin.rst (189, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.route_design.end.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.vivado.begin.rst (188, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.vivado.end.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.write_bitstream.begin.rst (189, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\.write_bitstream.end.rst (0, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\ISEWrap.js (7308, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\ISEWrap.sh (1623, 2019-02-03)
clkdiv26\clkdiv26.runs\impl_1\clkdiv26.bit (2192116, 2019-02-03)
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