adder
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：398KB
下载次数：0
上传日期：2019-04-27 19:15:54
上 传 者：
副主任
说明： 实现一位加法器，用于basys3开发板，将管教重新分配，可以适用于所有的开发板
(one bit full adder, designed for basys3 board, you can change the footprint nember to suit other board!)
文件列表:
adder\adder.cache\wt\java_command_handlers.wdf (291, 2018-06-13)
adder\adder.cache\wt\project.wpc (61, 2018-06-13)
adder\adder.cache\wt\synthesis.wdf (3739, 2018-06-13)
adder\adder.cache\wt\synthesis_details.wdf (100, 2018-06-13)
adder\adder.cache\wt\webtalk_pa.xml (1482, 2018-06-13)
adder\adder.cache\wt\xsim.wdf (256, 2018-06-13)
adder\adder.hw\adder.lpr (290, 2018-06-13)
adder\adder.runs\.jobs\vrs_config_1.xml (205, 2018-06-13)
adder\adder.runs\.jobs\vrs_config_2.xml (219, 2018-06-13)
adder\adder.runs\.jobs\vrs_config_3.xml (226, 2018-06-13)
adder\adder.runs\impl_1\.init_design.begin.rst (182, 2018-06-13)
adder\adder.runs\impl_1\.init_design.end.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.opt_design.begin.rst (182, 2018-06-13)
adder\adder.runs\impl_1\.opt_design.end.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.place_design.begin.rst (182, 2018-06-13)
adder\adder.runs\impl_1\.place_design.end.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.route_design.begin.rst (182, 2018-06-13)
adder\adder.runs\impl_1\.route_design.end.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.vivado.begin.rst (362, 2018-06-13)
adder\adder.runs\impl_1\.vivado.end.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.vivado.error.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.Vivado_Implementation.queue.rst (0, 2018-06-13)
adder\adder.runs\impl_1\.write_bitstream.begin.rst (182, 2018-06-13)
adder\adder.runs\impl_1\.write_bitstream.error.rst (0, 2018-06-13)
adder\adder.runs\impl_1\adder.dcp (8150, 2018-06-13)
adder\adder.runs\impl_1\adder.tcl (1759, 2018-06-13)
adder\adder.runs\impl_1\adder.vdi (20903, 2018-06-13)
adder\adder.runs\impl_1\adder_18104.backup.vdi (15914, 2018-06-13)
adder\adder.runs\impl_1\adder_clock_utilization_routed.rpt (5223, 2018-06-13)
adder\adder.runs\impl_1\adder_control_sets_placed.rpt (2569, 2018-06-13)
adder\adder.runs\impl_1\adder_drc_opted.rpt (3604, 2018-06-13)
adder\adder.runs\impl_1\adder_drc_routed.pb (37, 2018-06-13)
adder\adder.runs\impl_1\adder_drc_routed.rpt (3604, 2018-06-13)
adder\adder.runs\impl_1\adder_io_placed.rpt (61497, 2018-06-13)
adder\adder.runs\impl_1\adder_opt.dcp (8476, 2018-06-13)
adder\adder.runs\impl_1\adder_placed.dcp (116969, 2018-06-13)
adder\adder.runs\impl_1\adder_power_routed.rpt (6739, 2018-06-13)
adder\adder.runs\impl_1\adder_power_summary_routed.pb (675, 2018-06-13)
adder\adder.runs\impl_1\adder_routed.dcp (120523, 2018-06-13)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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