说明：  verilog经典学习教程 verilog HDL是一种用于数字系统设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型也称为模块。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言
(verilog Classic tutorial verilog HDL is a language for digital system design. Verilog HDL description with the circuit design is the circuit of the Verilog HDL model is also known as the module. Verilog HDL is both a language of behavior description and a language of structure description)