VHDL
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：17981KB
下载次数：3
上传日期：2019-05-09 00:07:12
上 传 者：
USTCer1322
说明： 先利用Matlab产生非负正弦波再采样1024点8位数据，保存到mystorage.mif。再在Quartus II 中利用MegaWizard生成一个1024*8bits的存储器（ram/rom），并利用上述正弦波数据来初始化此存储器。然后编写VHDL程序将数据输出到DA端口，编译及仿真。最后为工程添加一个signaltap II文件，设置参数，编译，无错后下载到目标板，并在signaltap II中观看输出到DA端口的数据及波形。
(First use Matlab to generate a non-negative sine wave and then sample 1024 points and 8 bits of data, and save it to mystorage.mif. Then use the MegaWizard in Quartus ll to generate a 1024*8bits memory (ram/rom) and initialize the memory with the above sine wave data. Then write the VHDL program to output the data to the DA port, compile and simulate. Finally, add a signaltapl file for the project, set the parameters, compile, download to the target board without error, and watch the data and waveform output to the DA port in signaltap ll.)
文件列表:
c5_pin_model_dump.txt (2857, 2019-04-23)
cio_dump_disallowed_lists.echo (53139, 2019-04-23)
db (0, 2019-04-23)
db\altsyncram_q484.tdf (15878, 2019-04-23)
db\altsyncram_urf1.tdf (10475, 2019-04-23)
db\cmpr_99c.tdf (1681, 2019-04-23)
db\cmpr_c9c.tdf (1913, 2019-04-23)
db\cmpr_d9c.tdf (2003, 2019-04-23)
db\cntr_29i.tdf (4248, 2019-04-23)
db\cntr_82j.tdf (4836, 2019-04-23)
db\cntr_j7i.tdf (4081, 2019-04-23)
db\cntr_kri.tdf (3542, 2019-04-23)
db\decode_vnf.tdf (1562, 2019-04-23)
db\FPGA_EXP5.(0).cnf.cdb (2406, 2019-04-23)
db\FPGA_EXP5.(0).cnf.hdb (1032, 2019-04-23)
db\FPGA_EXP5.(1).cnf.cdb (1563, 2019-04-23)
db\FPGA_EXP5.(1).cnf.hdb (944, 2019-04-23)
db\FPGA_EXP5.(10).cnf.cdb (4031, 2019-04-23)
db\FPGA_EXP5.(10).cnf.hdb (785, 2019-04-23)
db\FPGA_EXP5.(11).cnf.cdb (2439, 2019-04-23)
db\FPGA_EXP5.(11).cnf.hdb (1577, 2019-04-23)
db\FPGA_EXP5.(12).cnf.cdb (1477, 2019-04-23)
db\FPGA_EXP5.(12).cnf.hdb (800, 2019-04-23)
db\FPGA_EXP5.(13).cnf.cdb (1752, 2019-04-23)
db\FPGA_EXP5.(13).cnf.hdb (1452, 2019-04-23)
db\FPGA_EXP5.(14).cnf.cdb (2505, 2019-04-23)
db\FPGA_EXP5.(14).cnf.hdb (714, 2019-04-23)
db\FPGA_EXP5.(15).cnf.cdb (11362, 2019-04-23)
db\FPGA_EXP5.(15).cnf.hdb (2826, 2019-04-23)
db\FPGA_EXP5.(16).cnf.cdb (2739, 2019-04-23)
db\FPGA_EXP5.(16).cnf.hdb (728, 2019-04-23)
db\FPGA_EXP5.(17).cnf.cdb (1792, 2019-04-23)
db\FPGA_EXP5.(17).cnf.hdb (805, 2019-04-23)
db\FPGA_EXP5.(18).cnf.cdb (2367, 2019-04-23)
db\FPGA_EXP5.(18).cnf.hdb (898, 2019-04-23)
db\FPGA_EXP5.(19).cnf.cdb (4574, 2019-04-23)
db\FPGA_EXP5.(19).cnf.hdb (1220, 2019-04-23)
db\FPGA_EXP5.(2).cnf.cdb (1440, 2019-04-23)
db\FPGA_EXP5.(2).cnf.hdb (780, 2019-04-23)
db\FPGA_EXP5.(20).cnf.cdb (1703, 2019-04-23)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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