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STM32H7_ADC_DIFF_TEST20190422\BSP\Adafruit_Shield\Release_Notes.html (21321, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Adafruit_Shield\stm32_adafruit_lcd.c (29851, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Adafruit_Shield\stm32_adafruit_lcd.h (6209, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Adafruit_Shield\stm32_adafruit_sd.c (35284, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Adafruit_Shield\stm32_adafruit_sd.h (8418, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\adv7533\adv7533.c (14905, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\adv7533\adv7533.h (7893, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\adv7533\Release_Notes.html (14416, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ampire480272\ampire480272.h (4004, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ampire480272\Release_Notes.html (13885, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ampire640480\ampire640480.h (4028, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ampire640480\Release_Notes.html (13696, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\accelero.h (4681, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\audio.h (3682, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\camera.h (5447, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\epd.h (3389, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\gyro.h (4661, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\idd.h (6628, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\io.h (5449, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\lcd.h (3638, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\magneto.h (3662, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\Release_Notes.html (33316, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\ts.h (3297, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\Common\tsensor.h (3727, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\exc7200\exc7200.c (6763, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\exc7200\exc7200.h (4416, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\exc7200\Release_Notes.html (13575, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ft5336\ft5336.c (19550, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ft5336\ft5336.h (20633, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ft5336\Release_Notes.html (14068, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ft6x06\ft6x06.c (16775, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ft6x06\ft6x06.h (15580, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\ft6x06\Release_Notes.html (12774, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\lan8742\lan8742.c (20600, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\lan8742\lan8742.h (17279, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\lan8742\Release_Notes.html (12825, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\mfxstm32l152\mfxstm32l152.c (59549, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\mfxstm32l152\mfxstm32l152.h (26730, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\mfxstm32l152\Release_Notes.html (16980, 2018-07-04)
STM32H7_ADC_DIFF_TEST20190422\BSP\Components\mt25tl01g\mt25tl01g.h (10747, 2018-07-04)
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/** @page ADC_DMA_Transfer ADC DMA Transfer example @verbatim ******************** (C) COPYRIGHT 2017 STMicroelectronics ******************* * @file ADC/ADC_DMA_Transfer/readme.txt * @author MCD Application Team * @brief Description of the ADC DMA Transfer example. ****************************************************************************** * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** @endverbatim @par Example Description This example describes how to configure and use the ADC to convert an external analog input and get the result using a DMA transfer through the HAL API. At the beginning of the main program the HAL_Init() function is called to reset all the peripherals, initialize the Flash interface and the systick. The SystemClock_Config() function is used to configure the system clock for STM32H743xx Devices : The CPU at 400MHz The HCLK for D1 Domain AXI and AHB3 peripherals , D2 Domain AHB1/AHB2 peripherals and D3 Domain AHB4 peripherals at 200MHz. The APB clock dividers for D1 Domain APB3 peripherals, D2 Domain APB1 and APB2 peripherals and D3 Domain APB4 peripherals to run at 100MHz The ADC is configured to convert continuously ADC_CHANNEL_3, resolution is set to 16 bits right aligned, conversion is software-triggered. DMA1_Stream1 is configured in Circular mode to transfer continuously the content of ADC_DR (Data Register) to "aADCxConvertedData" variable which stores the conversion result. User may watch variable array "aADCxConvertedData" and check that its values are modified according to the voltage applied to pin PA.06 (connector CN12 pin 13). STM32 board LED can be used to monitor the conversion: - LED3 is ON when there is an error in initialization. @note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds) based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function. @note The example need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation. @Note If the application is using the DTCM/ITCM memories (@0x20000000/ 0x0000000: not cacheable and only accessible by the Cortex M7 and the MDMA), no need for cache maintenance when the Cortex M7 and the MDMA access these RAMs. If the application needs to use DMA(or other masters) based access or requires more RAM, then the user has to: - Use a non TCM SRAM. (example : D1 AXI-SRAM @ 0x24000000) - Add a cache maintenance mechanism to ensure the cache coherence between CPU and other masters(DMAs,DMA2D,LTDC,MDMA). - The addresses and the size of cacheable buffers (shared between CPU and other masters) must be properlydefined to be aligned to L1-CACHE line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence, but depending on the use case It is also possible to configure the MPU as "Write through", to guarantee the write access coherence. In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable. Even though the user must manage the cache coherence for read accesses. Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs” Please refer to the AN4839 “Level 1 cache on STM32F7 Series” @par Directory contents - ADC/ADC_DMA_Transfer/Inc/stm32h7xx_hal_conf.h HAL configuration file - ADC/ADC_DMA_Transfer/Inc/stm32h7xx_it.h HAL interrupt handlers header file - ADC/ADC_DMA_Transfer/Inc/main.h Header for main.c module - ADC/ADC_DMA_Transfer/Src/stm32h7xx_it.c HAL interrupt handlers - ADC/ADC_DMA_Transfer/Src/main.c Main program - ADC/ADC_DMA_Transfer/Src/stm32h7xx_hal_msp.c HAL MSP file - ADC/ADC_DMA_Transfer/Src/system_stm32h7xx.c STM32H7xx system source file @par Hardware and Software environment - This example runs on STM32H743xx devices. - This example has been tested with STM32H743ZI-Nucleo board and can be easily tailored to any other supported device and development board. - STM32H743ZI-Nucleo Set-up Use an external power supply, adjust supply voltage and connect it to pin PA.06 (connector CN12 pin 13). - To monitor the conversion result, put the "aADCxConvertedData" variable in the debugger live watch. @par How to use it ? In order to make the program work, you must do the following : - Open your preferred toolchain - Rebuild all files and load your image into target memory - Run the example *

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