jtag
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：876KB
下载次数：8
上传日期：2019-05-21 17:39:36
上 传 者：
盒盒
说明： Jtag verilog code, this file with verilog language describes the functions of jtag
文件列表:
jtag\tags\arelease\ieee_1149.1_tap\BiDirectionalCell.v (2060, 2000-08-21)
jtag\tags\arelease\ieee_1149.1_tap\Boundary-Scan_Architecture.pdf (59372, 2000-08-21)
jtag\tags\arelease\ieee_1149.1_tap\ControlCell.v (3621, 2000-08-21)
jtag\tags\arelease\ieee_1149.1_tap\InputCell.v (3057, 2000-08-21)
jtag\tags\arelease\ieee_1149.1_tap\OutputCell.v (3864, 2000-08-21)
jtag\tags\arelease\ieee_1149.1_tap\TAP.v (18930, 2000-08-21)
jtag\tags\asyst_2\tap\rtl\verilog\tap_defines.v (3421, 2004-01-27)
jtag\tags\asyst_2\tap\rtl\verilog\tap_top.v (20511, 2004-01-27)
jtag\tags\asyst_3\tap\rtl\verilog\tap_defines.v (3421, 2004-01-27)
jtag\tags\asyst_3\tap\rtl\verilog\tap_top.v (20511, 2004-01-27)
jtag\tags\rel_1\doc\Boundary-Scan_Architecture.pdf (59372, 2003-12-23)
jtag\tags\rel_1\doc\or1k_10.bsd (5829, 2003-12-23)
jtag\tags\rel_1\tap\rtl\verilog\tap_defines.v (3374, 2003-12-23)
jtag\tags\rel_1\tap\rtl\verilog\tap_top.v (21536, 2004-01-14)
jtag\tags\rel_2\doc\Boundary-Scan_Architecture.pdf (59372, 2003-12-23)
jtag\tags\rel_2\doc\or1k_10.bsd (5829, 2003-12-23)
jtag\tags\rel_2\tap\rtl\verilog\tap_defines.v (3374, 2003-12-23)
jtag\tags\rel_2\tap\rtl\verilog\tap_top.v (21713, 2004-01-18)
jtag\tags\rel_3\tap\rtl\verilog\tap_defines.v (3374, 2003-12-23)
jtag\tags\rel_3\tap\rtl\verilog\tap_top.v (21789, 2004-01-18)
jtag\tags\rel_4\tap\rtl\verilog\tap_defines.v (3421, 2004-01-27)
jtag\tags\rel_4\tap\rtl\verilog\tap_top.v (20511, 2004-01-27)
jtag\tags\rel_5\cells\rtl\verilog\BiDirectionalCell.v (2060, 2003-12-23)
jtag\tags\rel_5\cells\rtl\verilog\ControlCell.v (3621, 2003-12-23)
jtag\tags\rel_5\cells\rtl\verilog\InputCell.v (3057, 2003-12-23)
jtag\tags\rel_5\cells\rtl\verilog\OutputCell.v (3864, 2003-12-23)
jtag\tags\rel_5\tap\doc\jtag.pdf (426802, 2004-02-02)
jtag\tags\rel_5\tap\doc\src\jtag.doc (244224, 2004-02-02)
jtag\tags\rel_5\tap\rtl\verilog\tap_defines.v (3421, 2004-01-27)
jtag\tags\rel_5\tap\rtl\verilog\tap_top.v (20511, 2004-01-27)
jtag\trunk\cells\rtl\verilog\BiDirectionalCell.v (2060, 2003-12-23)
jtag\trunk\cells\rtl\verilog\ControlCell.v (3621, 2003-12-23)
jtag\trunk\cells\rtl\verilog\InputCell.v (3057, 2003-12-23)
jtag\trunk\cells\rtl\verilog\OutputCell.v (3864, 2003-12-23)
jtag\trunk\tap\doc\jtag.pdf (426802, 2004-02-02)
jtag\trunk\tap\doc\src\jtag.doc (244224, 2004-02-02)
jtag\trunk\tap\rtl\verilog\tap_defines.v (3653, 2004-03-03)
jtag\trunk\tap\rtl\verilog\tap_top.v (20511, 2004-01-27)
jtag\web_uploads\Boundary-Scan Architecture.pdf (59372, 2009-03-10)
jtag\web_uploads\index.shtml (1887, 2009-03-10)
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