SystemVerilog-UART
所属分类:VHDL/FPGA/Verilog
开发工具:SystemVerilog
文件大小:10KB
下载次数:0
上传日期:2019-06-11 18:39:02
上 传 者:
sh-1993
说明: 简单的UART发射器和接收器
(Simple UART transmitter and receiver)
文件列表:
LICENSE (1066, 2019-06-12)
rtl (0, 2019-06-12)
rtl\if (0, 2019-06-12)
rtl\if\uart_if.sv (1520, 2019-06-12)
rtl\uart.sv (1837, 2019-06-12)
rtl\uart_rx.sv (6288, 2019-06-12)
rtl\uart_tx.sv (4701, 2019-06-12)
testbench (0, 2019-06-12)
testbench\uart_rx_tb.sv (3416, 2019-06-12)
testbench\uart_tx_tb.sv (3355, 2019-06-12)
# SystemVerilog-UART
Simple UART transmitter and receiver
## Feature
- You can freely specify the parameters that are baud rate, clock frequency and data width
- Interface are designed by VALID-READY handshake
- **NOT supported parity bit**
## License
MIT
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