shizizhong
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:249KB
下载次数:9
上传日期:2011-06-08 22:24:07
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shimaomaoss
说明: no intro
(QuartusII7.0, MATLAB, and SmartSOPC experimental system for the design of multi-function digital clock is the main content of the trial. The figure is included in the functions needed are: sub-band, school, when school hours, resetting, dynamic display, the whole point timekeeping, alarm clock alarm, stopwatch and 24-hour system and 12-hour system conversion.)
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shizizhong.docx (284354, 2010-03-21)
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