liteeth-master
所属分类：VHDL/FPGA/Verilog
开发工具：Python
文件大小：250KB
下载次数：0
上传日期：2019-07-16 01:09:31
上 传 者：
omidjoon
说明： LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.
Since Python is used to describe the HDL, the core is highly and easily
configurable.
文件列表:
CONTRIBUTORS (759, 2019-06-24)
LICENSE (1682, 2019-06-24)
doc (0, 2019-06-24)
doc\architecture.dia (3408, 2019-06-24)
doc\architecture.png (31809, 2019-06-24)
doc\enjoy_digital.png (4280, 2019-06-24)
doc\liteeth_logo_full.png (56337, 2019-06-24)
doc\liteeth_logo_full.svg (93602, 2019-06-24)
examples (0, 2019-06-24)
examples\__init__.py (0, 2019-06-24)
examples\make.py (5093, 2019-06-24)
examples\targets (0, 2019-06-24)
examples\targets\Makefile (621, 2019-06-24)
examples\targets\__init__.py (0, 2019-06-24)
examples\targets\base.py (5554, 2019-06-24)
examples\targets\core.py (9337, 2019-06-24)
examples\targets\etherbone.py (2532, 2019-06-24)
examples\targets\tty.py (1212, 2019-06-24)
examples\targets\udp.py (2056, 2019-06-24)
examples\test (0, 2019-06-24)
examples\test\test_analyzer.py (522, 2019-06-24)
examples\test\test_etherbone.py (1091, 2019-06-24)
examples\test\test_regs.py (503, 2019-06-24)
examples\test\test_tty.py (1045, 2019-06-24)
examples\test\test_udp.py (2336, 2019-06-24)
liteeth (0, 2019-06-24)
liteeth\__init__.py (0, 2019-06-24)
liteeth\common.py (8318, 2019-06-24)
liteeth\core (0, 2019-06-24)
liteeth\core\__init__.py (975, 2019-06-24)
liteeth\core\arp.py (10659, 2019-06-24)
liteeth\core\icmp.py (5270, 2019-06-24)
liteeth\core\ip.py (9205, 2019-06-24)
liteeth\core\mac.py (63, 2019-06-24)
liteeth\core\udp.py (7201, 2019-06-24)
liteeth\crossbar.py (1255, 2019-06-24)
liteeth\frontend (0, 2019-06-24)
... ...
__ _ __ ______ __
/ / (_) /____ / __/ /_/ /
/ /__/ / __/ -_) _// __/ _ \
/____/_/\__/\__/___/\__/_//_/
Copyright 2012-2018 / EnjoyDigital
A small footprint and configurable Ethernet core
powered by LiteX & Migen
[> Intro
--------
LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Using Migen to describe the HDL allows the core to be highly and easily configurable.
LiteEth can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
[> Features
-----------
PHY:
- MII, RMII 100Mbps PHYs.
- GMII / RGMII /1000BaseX 1Gbps PHYs.
Core:
- Configurable MAC (HW or SW interface)
- ARP / ICMP / UDP (HW or SW)
Frontend:
- Etherbone (Wishbone over UDP: Slave or Master support)
[> FPGA Proven
---------------
LiteEth is already used in commercial and open-source designs:
- MiSoC: http://m-labs.hk/gateware.html
- ARTIQ: http://m-labs.hk/artiq/index.html
- HDMI2USB: http://hdmi2usb.tv/home/
- and others commercial designs...
[> Possible improvements
------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add DMA interface to MAC
- add more documentation
- ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr.
[> Getting started
------------------
1. Install Python 3.5, Migen and FPGA vendor's development tools.
Get Migen from: https://github.com/m-labs/migen
2. Obtain LiteX and install it:
git clone https://github.com/enjoy-digital/litex --recursive
cd litex
python3 setup.py develop
cd ..
3. TODO: add/describe examples
[> Tests
--------
Unit tests are available in ./test/.
To run all the unit tests:
./setup.py test
Tests can also be run individually:
python3 -m unittest test.test_name
[> License
----------
LiteEth is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteEth for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
- tell us that you are using LiteEth
- cite LiteEth in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteEth.
[> Support and consulting
-------------------------
We love open-source hardware and like sharing our designs with others.
LiteEth is developed and maintained by EnjoyDigital.
If you would like to know more about LiteEth or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)
[> Contact
----------
E-mail: florent [AT] enjoy-digital.fr
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