litepcie-master
所属分类：VHDL/FPGA/Verilog
开发工具：Python
文件大小：488KB
下载次数：1
上传日期：2019-07-16 01:12:48
上 传 者：
omidjoon
说明： LitePCIe provides a small footprint and configurable PCIe core.
LitePCIe is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Using Migen to describe the HDL allows the core to be highly and easily configurable.
LitePCIe can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
文件列表:
CONTRIBUTORS (623, 2019-07-11)
LICENSE (1683, 2019-07-11)
MANIFEST.in (26, 2019-07-11)
doc (0, 2019-07-11)
doc\architecture.dia (3617, 2019-07-11)
doc\architecture.png (31230, 2019-07-11)
doc\enjoy_digital.png (4280, 2019-07-11)
doc\litepcie_logo_full.png (58494, 2019-07-11)
doc\litepcie_logo_full.svg (92801, 2019-07-11)
examples (0, 2019-07-11)
examples\__init__.py (0, 2019-07-11)
examples\make.py (5386, 2019-07-11)
examples\targets (0, 2019-07-11)
examples\targets\__init__.py (0, 2019-07-11)
examples\targets\dma.py (2538, 2019-07-11)
examples\test (0, 2019-07-11)
examples\test\test_regs.py (808, 2019-07-11)
litepcie (0, 2019-07-11)
litepcie\__init__.py (0, 2019-07-11)
litepcie\common.py (1837, 2019-07-11)
litepcie\core (0, 2019-07-11)
litepcie\core\__init__.py (94, 2019-07-11)
litepcie\core\common.py (1112, 2019-07-11)
litepcie\core\crossbar.py (5459, 2019-07-11)
litepcie\core\endpoint.py (1562, 2019-07-11)
litepcie\core\msi.py (1365, 2019-07-11)
litepcie\core\tlp (0, 2019-07-11)
litepcie\core\tlp\__init__.py (0, 2019-07-11)
litepcie\core\tlp\common.py (3431, 2019-07-11)
litepcie\core\tlp\controller.py (5762, 2019-07-11)
litepcie\core\tlp\depacketizer.py (8473, 2019-07-11)
litepcie\core\tlp\packetizer.py (9529, 2019-07-11)
litepcie\frontend (0, 2019-07-11)
litepcie\frontend\__init__.py (0, 2019-07-11)
litepcie\frontend\dma.py (16178, 2019-07-11)
litepcie\frontend\wishbone.py (2570, 2019-07-11)
litepcie\phy (0, 2019-07-11)
... ...
__ _ __ ___ _________
/ / (_) /____ / _ \/ ___/ _/__
/ /__/ / __/ -_) ___/ /___/ // -_)
/____/_/\__/\__/_/ \___/___/\__/
Copyright 2015-2019 / EnjoyDigital
A small footprint and configurable PCIe core
powered by Migen & LiteX
[> Intro
--------
LitePCIe provides a small footprint and configurable PCIe core.
LitePCIe is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Using Migen to describe the HDL allows the core to be highly and easily configurable.
LitePCIe can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
[> Features
-----------
PHY:
- Xilinx 7-Series (up to PCIe Gen2 X4)
- Intel Cyclone5 (up to PCIe Gen2 X4)
Core:
- TLP layer
- Reordering
Frontend:
- DMA (with Scatter-Gather)
- Wishbone bridge
Software:
- Linux Driver (DMA and Sysfs)
[> FPGA Proven
---------------
LitePCIe is already used in commercial and open-source designs:
- PCIe SDR MIMO 2x2: https://www.amarisoft.com/products-lte-ue-ots-sdr-pcie/#sdr
- PCIe TLP sniffer/injector: https://ramtin-amin.fr/#nvmedma
- and others commercial designs...
[> Possible improvements
------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add support for PCIe Gen2 X8
- add Xilinx Ultrascale support
- add Intel Stratix support
- add Lattice support
- add more documentation
- ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr.
[> Getting started
------------------
1. Install Python 3.5, Migen and FPGA vendor's development tools.
Get Migen from: https://github.com/m-labs/migen
2. Obtain LiteX and install it:
git clone https://github.com/enjoy-digital/litex --recursive
cd litex
python3 setup.py develop
cd ..
3. TODO: add/describe examples
[> Tests
--------
Unit tests are available in ./test/.
To run all the unit tests:
./setup.py test
Tests can also be run individually:
python3 -m unittest test.test_name
[> License
----------
LitePCIe is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteEth for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
- tell us that you are using LitePCIe
- cite LitePCIe in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LitePCIe.
[> Support and consulting
-------------------------
We love open-source hardware and like sharing our designs with others.
LitePCIe is developed and maintained by EnjoyDigital.
If you would like to know more about LitePCIe or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)
[> Contact
----------
E-mail: florent [AT] enjoy-digital.fr
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