BPSK
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：6583KB
下载次数：9
上传日期：2019-08-02 12:48:04
上 传 者：
劉劉劉
说明： 先用Matlab理论仿真，再用Verilog语言在ISE环境下编写程序，可通过手机发送指令来控制上下变频器的参数。
(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)
文件列表:
BPSK\aaa.m (59, 2019-05-07)
BPSK\BPSK.m (3519, 2019-06-17)
BPSK\BPSK_Signal.cmd_log (317, 2019-05-06)
BPSK\BPSK_Signal.v (1922, 2019-05-08)
BPSK\BSK.coe (845, 2019-05-08)
BPSK\B_H.coe (855, 2019-05-08)
BPSK\B_L.coe (845, 2019-05-08)
BPSK\CXD301.ucf (8465, 2019-05-07)
BPSK\FIR_BPSK.mif (1148, 2019-05-07)
BPSK\FIR_BPSKCOEFF_auto0_0.mif (126, 2019-05-07)
BPSK\FIR_BPSKCOEFF_auto0_1.mif (126, 2019-05-07)
BPSK\FIR_BPSKCOEFF_auto0_2.mif (126, 2019-05-07)
BPSK\FIR_BPSKCOEFF_auto0_3.mif (126, 2019-05-07)
BPSK\FIR_BPSKCOEFF_auto0_4.mif (126, 2019-05-07)
BPSK\FIR_BPSKCOEFF_auto0_5.mif (126, 2019-05-07)
BPSK\FIR_BPSKfilt_decode_rom.mif (85, 2019-05-07)
BPSK\FIR_High.mif (854, 2019-05-06)
BPSK\FIR_HighCOEFF_auto0_0.mif (126, 2019-05-06)
BPSK\FIR_HighCOEFF_auto0_1.mif (126, 2019-05-06)
BPSK\FIR_HighCOEFF_auto0_2.mif (126, 2019-05-06)
BPSK\FIR_HighCOEFF_auto0_3.mif (126, 2019-05-06)
BPSK\FIR_Highfilt_decode_rom.mif (85, 2019-05-06)
BPSK\FIR_Low.mif (1148, 2019-05-07)
BPSK\FIR_LowCOEFF_auto0_0.mif (126, 2019-05-07)
BPSK\FIR_LowCOEFF_auto0_1.mif (126, 2019-05-07)
BPSK\FIR_LowCOEFF_auto0_2.mif (126, 2019-05-07)
BPSK\FIR_LowCOEFF_auto0_3.mif (126, 2019-05-07)
BPSK\FIR_LowCOEFF_auto0_4.mif (126, 2019-05-07)
BPSK\FIR_LowCOEFF_auto0_5.mif (126, 2019-05-07)
BPSK\FIR_Lowfilt_decode_rom.mif (85, 2019-05-07)
BPSK\integrated_design.bgn (8010, 2019-06-17)
BPSK\integrated_design.bit (464872, 2019-06-17)
BPSK\Integrated_Design.bld (1509, 2019-06-17)
BPSK\Integrated_Design.cmd_log (889, 2019-06-17)
BPSK\integrated_design.drc (1186, 2019-06-17)
BPSK\Integrated_Design.lso (6, 2019-06-17)
BPSK\Integrated_Design.ncd (597345, 2019-06-17)
BPSK\Integrated_Design.ngc (79380, 2019-06-17)
BPSK\Integrated_Design.ngd (1639608, 2019-06-17)
BPSK\Integrated_Design.ngr (73164, 2019-06-17)
... ...
The following files were generated for 'Sin_1M' in directory
C:\Users\Lenovo\Desktop\FPGA\1. FPGA Practice\Week11\Integrated_Design\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* Sin_1M.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* Sin_1M.ngc
Obfuscate Netlist Generator:
Please see the core data sheet.
* Sin_1M.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* Sin_1M.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* Sin_1M.v
All Documents Generator:
Please see the core data sheet.
* Sin_1M/doc/dds_compiler_v4_0_vinfo.html
* Sin_1M/doc/dds_ds558.pdf
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* Sin_1M.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* Sin_1M.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* Sin_1M_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* Sin_1M.gise
* Sin_1M.xise
* _xmsgs/pn_parser.xmsgs
* xhdp.ini
* xilinxsim.ini
Deliver Readme:
Readme file for the IP.
* Sin_1M_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* Sin_1M_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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