s32k144_devices
所属分类:其他
开发工具:C/C++
文件大小:231KB
下载次数:3
上传日期:2019-10-11 16:14:28
上 传 者:
zhaoliangyan9399
说明: S32K144_devices,为S32K144_devices开发提供帮助
(S32K144_devices,Help with S32K144_devices development)
文件列表:
s32k144_devices\common\s32_core_cm4.h (6981, 2016-12-23)
s32k144_devices\devassert.h (4930, 2016-12-23)
s32k144_devices\device_registers.h (3709, 2016-12-23)
s32k144_devices\S32K144\doxygen\s32k144.dox (1225, 2016-12-23)
s32k144_devices\S32K144\include\S32K144.h (740065, 2016-12-23)
s32k144_devices\S32K144\include\S32K144_features.h (51166, 2016-12-23)
s32k144_devices\S32K144\linker\csmc\S32K144_48_flash.lkf (4681, 2016-12-23)
s32k144_devices\S32K144\linker\csmc\S32K144_48_ram.lkf (4103, 2016-12-23)
s32k144_devices\S32K144\linker\csmc\S32K144_64_flash.lkf (4681, 2016-12-23)
s32k144_devices\S32K144\linker\csmc\S32K144_64_ram.lkf (4103, 2016-12-23)
s32k144_devices\S32K144\linker\dcc\S32K144_48_flash.dld (5845, 2016-12-23)
s32k144_devices\S32K144\linker\dcc\S32K144_48_ram.dld (4980, 2016-12-23)
s32k144_devices\S32K144\linker\dcc\S32K144_64_flash.dld (5845, 2016-12-23)
s32k144_devices\S32K144\linker\dcc\S32K144_64_ram.dld (4980, 2016-12-23)
s32k144_devices\S32K144\linker\gcc\S32K144_48_flash.ld (8861, 2016-12-23)
s32k144_devices\S32K144\linker\gcc\S32K144_48_ram.ld (7618, 2016-12-23)
s32k144_devices\S32K144\linker\gcc\S32K144_64_flash.ld (8861, 2016-12-23)
s32k144_devices\S32K144\linker\gcc\S32K144_64_ram.ld (7618, 2016-12-23)
s32k144_devices\S32K144\linker\ghs\S32K144_48_flash.ld (7717, 2016-12-23)
s32k144_devices\S32K144\linker\ghs\S32K144_48_ram.ld (6452, 2016-12-23)
s32k144_devices\S32K144\linker\ghs\S32K144_64_flash.ld (7717, 2016-12-23)
s32k144_devices\S32K144\linker\ghs\S32K144_64_ram.ld (6452, 2016-12-23)
s32k144_devices\S32K144\linker\iar\S32K144_48_flash.icf (6396, 2016-12-23)
s32k144_devices\S32K144\linker\iar\S32K144_48_ram.icf (4597, 2016-12-23)
s32k144_devices\S32K144\linker\iar\S32K144_64_flash.icf (6396, 2016-12-23)
s32k144_devices\S32K144\linker\iar\S32K144_64_ram.icf (4597, 2016-12-23)
s32k144_devices\S32K144\S32K144.svd (6066954, 2016-12-23)
s32k144_devices\S32K144\startup\csmc\startup_S32K144.s (29709, 2016-12-23)
s32k144_devices\S32K144\startup\dcc\startup_S32K144.s (29700, 2016-12-23)
s32k144_devices\S32K144\startup\gcc\startup_S32K144.S (32128, 2016-12-23)
s32k144_devices\S32K144\startup\ghs\startup_S32K144.s (29798, 2016-12-23)
s32k144_devices\S32K144\startup\iar\startup_S32K144.s (32953, 2016-12-23)
s32k144_devices\S32K144\startup\system_S32K144.c (10206, 2016-12-23)
s32k144_devices\S32K144\startup\system_S32K144.h (5860, 2016-12-23)
s32k144_devices\startup.c (7351, 2016-12-23)
s32k144_devices\startup.h (2327, 2016-12-23)
s32k144_devices\status.h (7296, 2016-12-23)
s32k144_devices\S32K144\linker\csmc (0, 2017-03-02)
s32k144_devices\S32K144\linker\dcc (0, 2017-03-02)
... ...
/**
** @ingroup soc_header
** @defgroup soc_header_usage Header File Usage
** @{
**
** ## Introduction ##
**
** The following lines describe our recommendations of usage for the S32SDK
** header files that are supposed to improve both code reuse and code
** portability.\n
** It presents typical use cases such as:
** - 1. Initialize register
** - 2. Initialize bit / bit-field
** - 3. Set bit-field in register
** - 4. Clear bit-field in register
** - 5. Read bit / bit-field
** - 6. Initialize bit using read/modify/write solution
** - 7. Modifying register values when at least 1 bit is w1c
** - 8. Using Interrupts
** .
** Any assignement of a hardcoded value is highly discouraged. It is recommended
** the usage of variables or macros for code consistency and reuse reasons.\n
** Information contained in the Header Files:
** - Interrupt vector numbers\n
** Example:
** @code
** HardFault_IRQn = -13
** MemoryManagement_IRQn = -12
** BusFault_IRQn = -11
** ...
** @endcode
**
** - Peripheral device memory map\n
** Example:
** @code
** typedef struct {
** ...
** __IO uint32_t YOFS;
** __IO uint32_t G;
** __IO uint32_t UG;
** __IO uint32_t CLPS;
** ...
** } ADC_Type, *ADC_MemMapPtr;
** @endcode
**
** - Peripheral device register access macros:\n
** + a macro which speecifies the bit-field mask
** + a macro which speecifies the bit-field offset
** + a macro which speecifies the bit-field width
** + a macro which maps a value to a bit-field
** .
** Example:
** @code
** #define ADC_YOFS_YOFS_MASK 0xFFu
** #define ADC_YOFS_YOFS_SHIFT 0u
** #define ADC_YOFS_YOFS_WIDTH 8u
** #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))< General form:
** @code
** _BASE_PTRS->regName = value;
** @endcode
**
** Example:
** @code
** #define PIN_PTR 5U
** PORTC->PCR[PIN_PTR] = regValue;
** @endcode
**
** ### 2. Initialize bit / bit-field \n###
**
** This method is used for initializing a bit or bit-field.\n
** The benefit of using this method is that modifications of register addresses
** or bit-field offsets will not require code changes when this method is used.
** \n
** General form:
** @code
** _BASE_PTRS->regName &= ~MASK;
** _BASE_PTRS->regName |= (value << SHIFT) & MASK;
** @endcode
**
** Example:
** @code
** #define PIN_IDX 5U
** GPIO_PORT->PTOR &= ~GPIO_PTOR_PTTO_MASK;
** GPIO_PORT->PTOR |= GPIO_PTOR_PTTO(PIN_IDX);
** @endcode
**
** ### 3. Set bit-field in register \n###
**
** This method is used to perform a bitwise OR between a bit-field and a given
** value.\n
**
** General form:
** @code
** _BASE_PTRS->regName |= (value << shift) & MASK ;
** @endcode
**
** Example:
** @code
** GPIO_PORT->PTOR |= (value << GPIO_PTOR_PTTO_SHIFT) & GPIO_PTOR_PTTO_MASK;
** @endcode
**
** ### 4. Clear bit-field in register \n###
**
** This method is used for clearing a bit-field in a register.\n
** For registers where there is at least one w1c bit please see section 8.\n
**
** General form:
** @code
** _BASE_PTRS->regName &= ~MASK;
** @endcode
**
** Example:
** @code
** GPIO_PORT->PTOR &= ~GPIO_PTOR_PTTO_MASK;
** @endcode
**
** ### 5. Read bit / bit-field \n###
**
** This method is used for reading the value of a bit-field from a register.
**
** General form:
** @code
** x = (_BASE_PTRS->regName & mask) >> shift
** @endcode
**
** Example:
** @code
** pcr_mux_value = (base->PCR[pin] & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT;
** @endcode
**
** ### 6. Initialize bit using read/modify/write solution ###
**
** This method is used for clearing / setting a value to a bit in a
** register taking into consideration the previous value.\n
** For w1c bits please consult section 8.
**
** General form:
** @code
** regValue = _BASE_PTRS->regName;
** regValue &= ~MASK;
** regValue |= (value << shift) & MASK;
** _BASE_PTRS->regName = regValue;
** @endcode
**
** Example:
** @code
** regValue = base->PCR[pin];
** regValue &= ~(PORT_PCR_MUX_MASK);
** regValue |= PORT_PCR_MUX(pcr_mux_value);
** base->PCR[pin] = regValue;
** @endcode
**
** ### 7. Modifying register values when at least 1 bit is w1c \n###
** When a register has at least one W1C bit different approaches are suggested
** depending on each particular case:
** - clearing a w1c bit in registers where there are only w1c bits\n
** For this case it is recommended that the bit mask is written at the
** register address.\n
** General form:
** @code
** _BASE_PTRS->regName = MASK;
** @endcode
**
** Example:
** @code
** LPI2C_BASE_PTRS->MSR = LPI2C_MSR_RDF_MASK;
** @endcode
**
** - clearing a w1c bit in registers where there are also "normal" bits\n
** For this case it is recommended that a read-modify-write method is
** used with the mask of the bit-field that will leave the values of
** the other bits unchanged.\n
** General form:
** @code
** _BASE_PTRS->regName |= MASK;
** @endcode
**
** Example:
** @code
** CMP_BASE_PTRS->C0 |= CMP_C0_CFF_MASK;
** @endcode
**
** - clearing a "normal" bit-field in registers where there are also w1c
** bits \n
** For this case it is recommended that a special mask is applied to
** the register. The mask should be created by applying an AND
** operation between the negated mask of the bit-field that is
** intended to be cleared and the negated masks of all the w1c
** bit-fields.\n
** General form:
** @code
** MASK = ~BITFIELD_MASK & ~W1C_BITFIELDS_MASKS
** _BASE_PTRS->regName &= MASK;
** @endcode
**
** Example:
** @code
** MASK = ~CMP_C0_SE_MASK & (~CMP_C0_CFR_MASK & ~CMP_C0_CFF_MASK);
** CMP_BASE_PTRS->C0 &= MASK;
** @endcode
**
** - setting a "normal" bit-field in registers where there are also w1c
** bits \n
** For this case it is recommended that a clearing is done as in the
** previous step and then the bit-field is set as in step 3\n
** General form:
** @code
** MASK = ~BITFIELD_MASK & ~W1C_BITFIELDS_MASKS
** _BASE_PTRS->regName &= MASK;
** _BASE_PTRS->regName |= (value << shift) & MASK;
** @endcode
**
** Example:
** @code
** MASK = ~CMP_C0_SE_MASK & (~CMP_C0_CFR_MASK & ~CMP_C0_CFF_MASK);
** CMP_BASE_PTRS->C0 &= MASK;
** CMP_BASE_PTRS->C0 |= (value< Example: \n
** Enable WakeUp interrupt for instance = 0
** @code
** uint32_t instance = 0;
**
** const IRQn_Type g_flexcanWakeUpIrqId[] = CAN_Wake_Up_IRQS;
**
** INT_SYS_EnableIRQ(g_flexcanWakeUpIrqId[instance]);
** @endcode
**
** @}
*/
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