说明：  VHDL教程，硬件描述语言是硬件设计人员和电子设计自动化工具之间的界面，其主要目的是用来编写设计文件建立电子系统行为级的仿真模
(Hardware description language is the interface between hardware designer and electronic design automation tool. Its main purpose is to write design documents and establish the simulation model of electronic system behavior level.)