数字逻辑基础与Verilog设计
所属分类：VHDL/FPGA/Verilog
开发工具：LINUX
文件大小：22570KB
下载次数：3
上传日期：2019-10-31 11:11:03
上 传 者：
lt001001
说明： A good FPGA learning book, you can download it and study hard
文件列表:
数字逻辑基础与Verilog设计\数字逻辑基础与Verilog设计（原书第2版）.pdf (16041481, 2009-07-09)
数字逻辑基础与Verilog设计\附录A.pdf (3886671, 2007-10-15)
数字逻辑基础与Verilog设计\附录B.pdf (5134368, 2007-10-15)
数字逻辑基础与Verilog设计\附录C.pdf (4426919, 2007-10-15)
数字逻辑基础与Verilog设计\附录D.pdf (708385, 2007-10-15)
数字逻辑基础与Verilog设计\附录E.pdf (2977089, 2007-10-15)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_11.v (448, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_12.v (277, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_13.v (457, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_14.v (273, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_18.v (555, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_19.v (698, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_2.v (169, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_20.v (466, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_21.v (504, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_22.v (370, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_23.v (535, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_24.v (573, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_25.v (730, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_26.v (602, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_27.v (127, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_28.v (125, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_29.v (209, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_3.v (126, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_30.v (193, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_31.v (201, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_32.v (221, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_33.v (261, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_34.v (186, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_35.v (183, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_36.v (220, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_38.v (1309, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_4.v (272, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_40.v (556, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_41.v (528, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_43.v (626, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_5.v (219, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_6.v (169, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_7.v (195, 2007-03-14)
数字逻辑基础与Verilog设计\Verilog_code\AppendixA\figA_9.v (171, 2007-03-14)
... ...
近期下载者：
相关文件：
收藏者：