FPGAandRS232-485VerilogSourcecode
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：113KB
下载次数：114
上传日期：2011-06-19 02:45:39
上 传 者：
Hi生先
说明： FPGA串行通信口RS232-485构建，RS232和485有选择控制，源程序基于QuartusII6.0用Verilog语言撰写。
(FPGA serial communication port RS232-485 build, RS232 and 485 to selectively control, source-based QuartusII6.0 written in Verilog language.)
文件列表:
db\add_sub_3rh.tdf (2271, 2010-09-27)
db\add_sub_4rh.tdf (2428, 2010-09-27)
db\add_sub_5rh.tdf (2585, 2010-09-27)
db\add_sub_8rh.tdf (3056, 2010-09-27)
db\altsyncram_fji2.tdf (16125, 2010-09-27)
db\altsyncram_hji2.tdf (17168, 2010-09-28)
db\cmpr_5mh.tdf (1548, 2010-09-27)
db\cntr_3jf.tdf (4054, 2010-09-27)
db\cntr_4ag.tdf (4029, 2010-09-27)
db\cntr_7he.tdf (4084, 2010-09-27)
db\cntr_8he.tdf (4084, 2010-09-28)
db\cntr_f7f.tdf (3872, 2010-09-27)
db\cntr_pdh.tdf (4274, 2010-09-27)
db\decode_ogi.tdf (3463, 2010-09-27)
db\mux_8ec.tdf (9967, 2010-09-27)
db\mux_jcc.tdf (2377, 2010-09-28)
db\mux_qfc.tdf (18968, 2010-09-27)
db\rs.db_info (137, 2011-06-18)
db\rs.eco.cdb (161, 2011-06-18)
db\rs.sim.vwf (16261, 2010-09-29)
db\rs.sld_design_entry.sci (527, 2011-06-18)
db\wed.wsf (2648, 2011-06-18)
db\wed.zsf (446, 2010-09-29)
div_clk.bsf (1578, 2010-09-27)
div_clk.v (264, 2010-09-29)
rs.bdf (6518, 2010-09-28)
rs.bsf (1641, 2010-09-28)
rs.cdf (294, 2010-09-28)
rs.qpf (902, 2010-09-27)
rs.vwf (5934, 2010-09-27)
rs.asm.rpt (7002, 2010-09-29)
rs.done (26, 2010-09-29)
rs.dpf (239, 2010-09-28)
rs.fit.rpt (142844, 2010-09-29)
rs.fit.smsg (411, 2010-09-29)
rs.fit.summary (403, 2010-09-29)
rs.flow.rpt (7965, 2010-09-29)
rs.map.rpt (129058, 2010-09-29)
rs.map.smsg (125, 2010-09-27)
rs.map.summary (314, 2010-09-29)
... ...
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