V5_512G_TLC_simulation model_181022

所属分类:嵌入式/单片机/硬件编程
开发工具:Verilog
文件大小:2698KB
下载次数:1
上传日期:2019-11-12 14:14:14
上 传 者Yannnnnnnnn
说明:  sk hynix v5 flash model

文件列表:
COM (0, 2018-10-22)
COM\AMS.env (1384, 2018-10-22)
COM\cds.liba (161, 2018-10-22)
COM\device.cfg (2451, 2018-10-22)
COM\hdl.var (209, 2018-10-22)
COM\Makefile (27414, 2018-10-22)
COM\modelsim.ini (85251, 2018-10-22)
COM\run_dbg.coma (96, 2018-10-22)
COM\run_ius.cmda (114, 2018-10-22)
COM\run_ms.cmda (62, 2018-10-22)
COM\run_vcs.cmda (146, 2018-10-22)
COM\ucli.key (137, 2018-10-22)
SKHYNIX_model_ms_encrypt.zip (275850, 2018-10-25)
SKHYNIX_model_nc_encrypt.zip (1236610, 2018-10-25)
SKHYNIX_model_vcs_encrypt.zip (1229564, 2018-10-25)

// **************************************************************************************************** // // *** This file contains all the run-time options & how to setup CE number and model instanciation *** // // **************************************************************************************************** // // ******** Simulation Version Information ********* // CAUTION!!! This verilog model contains system verilog syntex, thus user should use cadance INCISIVE version more than 11.xx Recommended Simulator Versions VCS: 2015.09 IES: 13.20.013 Questa: 10.5 // ******** Wrapper Information ********* // CAUTION!!! -> hynix_ce_model.sv, hynix_die_model,sv and tb.sv is SKHynix own wrapper for providing test scenario. -> Thus, user create user's own wrapper which dedicated to user's sysetm. or use model directly without wrapper. // ******** How to setup the number of CE & model instantiation ******** // 1. file name: model_nand_def.h -> Default number of setted CE are 2, and max number of CE is 8 -> create 1CE: `define _X_CE0 -> create 2CE: `define _X_CE0, `define _X_CE1 -> create 3CE: `define _X_CE0, `define _X_CE1, `define _X_CE2 -> create 4CE: `define _X_CE0, `define _X_CE1, `define _X_CE2, `define _X_CE3 -> create 5CE: `define _X_CE0, `define _X_CE1, `define _X_CE2, `define _X_CE3, `define _X_CE4 -> create 6CE: `define _X_CE0, `define _X_CE1, `define _X_CE2, `define _X_CE3, `define _X_CE4, `define _X_CE5 -> create 7CE: `define _X_CE0, `define _X_CE1, `define _X_CE2, `define _X_CE3, `define _X_CE4, `define _X_CE5, `define _X_CE6 -> create 8CE: `define _X_CE0, `define _X_CE1, `define _X_CE2, `define _X_CE3, `define _X_CE4, `define _X_CE5, `define _X_CE6, `define _X_CE7 2. you are able to select specific device & package type using model_nand_def.h -> In the file named model_nand_def.h, Package types for every device already created, and temporary commented out. -> User should enable one device, enable more than two device occurs errors -> User should choose device and package before compile, elaboration and simultion. -> how to instanciate specific device: Ex) QS***GMLC_B DDP model instantiate: - comment out `define _QS***GMLC_B_mod parameter selected_device = `HYNIX_F16B_DDP; - comment all other device QDP model instantiate: - comment out `define _QS***GMLC_B_mod parameter selected_device = `HYNIX_F16B_QDP; - comment all other device // ******** How to give simulation option ******** // for running simulation, you should give cfg file path and nand operation frequency as a simulation option You can look at the Makefile provided for better understandig with examples // ******** Mandatory options ******************** // 1. How to load timing_parameter configuration file run-time option -> $value$plusargs("CFG_PATH=%s", cfg_path) using example -> +CFG_PATH=$(your_model_path)/hynix 2. how to set nand_operation frequency run-time option -> $value$plusargs("HYNIX_NAND_IO_FREQ=%f", int_nand_freq) using example (toggle mode operation frequency 100 MHz) -> +HYNIX_NAND_IO_FREQ=100.0 // ******** Selective options ******************** // 3. txt file path for Unique ID(UID), Read parameter page(RPP), set/get parameter(SGPARA) // file name -> UID: uid.hex -> RPP: rpp.hex -> SGPARA: sgpara.hex run-time path option -> $value$plusargs("HYNIX_QS128GMLC_UID_PATH=%s", uid_path) -> $value$plusargs("HYNIX_QS128GMLC_RPP_PATH=%s", rpp_path) -> $value$plusargs("HYNIX_128GMLC_SGPARA_PATH=%s", sgpara_path) using example -> +HYNIX_QS128GMLC_UID_PATH=/user/hjyun/flash_model/hynix/QS128GMLC/uid.hex 4. verification module on/off option run-time option -> timing check on/off: $test$plusargs("DISABLE_TM_CHK") -> opcode check on/off: $test$plusargs("DISABLE_OP_CHK") using example -> add +DISABLE_TM_CHK for disable this option 5. timing check status display on/off option run-time option -> status display onoff: $test$plusargs("ASSERT_DEBUG") using example -> add +ASSERT_DEBUG for enable this option. 6. txt file path for BadBlock Mapping table. file name -> badblock.hex ex) s48 128gtlc (4plane) : "0004" means block(9'd1)/plane (2'b00) is badblock. run-time path option -> $value$plusargs("HYNIX_ZU128GTLC_BADBLOCK_PATH=%s", badblock_path) using example -> +HYNIX_ZU128GTLC_BADBLOCK_PATH=$(CUIRDIR)/../SRC/hynix/ZU128GTLC/badblock.hex

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