camera_ov7725_sample
所属分类：VHDL/FPGA/Verilog
开发工具：Vivado
文件大小：14737KB
下载次数：3
上传日期：2019-11-16 20:55:32
上 传 者：
beTTer_every
说明： 实现摄像头ov7725采集视频，通过vga端口输出.
fpga型号为EGO1，可以自行修改xdc文件.
(Realize the camera ov7725 acquisition of video, output through VGA port.
Fpga model EGO1, you can modify the XDC file.)
文件列表:
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\07936dd1d99345f0\07936dd1d99345f0.xci (3583, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\07936dd1d99345f0\cam_ov7670_ov7725_0.dcp (23447, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\07936dd1d99345f0\cam_ov7670_ov7725_0_sim_netlist.v (27152, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\07936dd1d99345f0\cam_ov7670_ov7725_0_sim_netlist.vhdl (34734, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\07936dd1d99345f0\cam_ov7670_ov7725_0_stub.v (1553, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\07936dd1d99345f0\cam_ov7670_ov7725_0_stub.vhdl (1778, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\3a159b54348a9a68\3a159b54348a9a68.xci (3923, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\3a159b54348a9a68\IICctrl_0.dcp (30717, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\3a159b54348a9a68\IICctrl_0_sim_netlist.v (45506, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\3a159b54348a9a68\IICctrl_0_sim_netlist.vhdl (57136, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\3a159b54348a9a68\IICctrl_0_stub.v (1491, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\3a159b54348a9a68\IICctrl_0_stub.vhdl (1642, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\579791e2fa813d36\579791e2fa813d36.xci (13112, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\579791e2fa813d36\blk_mem_gen_0.dcp (238171, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\579791e2fa813d36\blk_mem_gen_0_sim_netlist.v (698583, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\579791e2fa813d36\blk_mem_gen_0_sim_netlist.vhdl (776689, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\579791e2fa813d36\blk_mem_gen_0_stub.v (1471, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\579791e2fa813d36\blk_mem_gen_0_stub.vhdl (1673, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\8bdbfd78522ac0c2\8bdbfd78522ac0c2.xci (4197, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\8bdbfd78522ac0c2\ram_read_0.dcp (15788, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\8bdbfd78522ac0c2\ram_read_0_sim_netlist.v (14117, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\8bdbfd78522ac0c2\ram_read_0_sim_netlist.vhdl (16843, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\8bdbfd78522ac0c2\ram_read_0_stub.v (1600, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\8bdbfd78522ac0c2\ram_read_0_stub.vhdl (1824, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\d883790fc91b5490\d883790fc91b5490.xci (3657, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\d883790fc91b5490\vga_0.dcp (18094, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\d883790fc91b5490\vga_0_sim_netlist.v (22791, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\d883790fc91b5490\vga_0_sim_netlist.vhdl (28572, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\d883790fc91b5490\vga_0_stub.v (1420, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\d883790fc91b5490\vga_0_stub.vhdl (1571, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\dee7aaf119cce2f4\dee7aaf119cce2f4.xci (3815, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\dee7aaf119cce2f4\ov7725_regData_0.dcp (6568, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\dee7aaf119cce2f4\ov7725_regData_0_sim_netlist.v (5298, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\dee7aaf119cce2f4\ov7725_regData_0_sim_netlist.vhdl (5070, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\dee7aaf119cce2f4\ov7725_regData_0_stub.v (1383, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\dee7aaf119cce2f4\ov7725_regData_0_stub.vhdl (1522, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\e2b931c856e9b6d6\clk_wiz_0.dcp (9287, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\e2b931c856e9b6d6\clk_wiz_0_sim_netlist.v (7186, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\e2b931c856e9b6d6\clk_wiz_0_sim_netlist.vhdl (7220, 2019-11-09)
camera_ov7725_sample\camera_ov7725_sample\camera_ov7725_sample.cache\ip\2018.3\e2b931c856e9b6d6\clk_wiz_0_stub.v (1234, 2019-11-09)
... ...
Tool and version: Vivado 2014.4
Target Families: Artix-7, Kintex-7, Virtex-7, and Zynq
Introduction:
This interface IP generates timing signals (HSYNC, VSYNC, and Video Valid) along with horizontal and vertical positions. It provides configurable parameter of VGA standards. The standards supported are:
VGA- ***0x480 requiring 25 MHz pixel clock input
SVGA- 800x600 requiring 40 MHz pixel clock input
XVGA- 1024x768 requiring 65 MHz pixel clock input
SXGA- 1280x1024 requiring 108 MHz pixel clock input
Input/Output Ports:
Input:
pclk - varies depending on the TYPE
reset - high-level logic
Output:
hsync - Horizontal sync timing signal
vsync - Vertical sync timing signal
valid - viewable (or active) video
h_cnt[10:0] - current horizontal position of a pixel
v_cnt[10:0] - current vertical position of a pixel
Setting up the library path:
Create a Vivado project. Click on the Project Settings, then click on the IP block in the left panel, click on the Add Repository... button, browse to the directory where this IP directory is located, and click Select. The IP entry should be visible in the IP in the Selected Repository.
How to use the IP:
Step 1: Create a Vivado project
Step 2: Set the Project Settings to point to the IP path
Step 3: Create a block design
Step 4: Add the desired IP on the canvas, connect them, and add external input and output ports
Step 5: Create a HDL wrapper
Step 6: Add constraints file (.xdc)
Step 7: Synthesize, implement, and generate the bitstream
Step 8: Connect the board, download the bitstream, and varify the design
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