FreeAHB-master
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：903KB
下载次数：11
上传日期：2019-12-04 13:33:31
上 传 者：
dinuroy
说明： ahb master using verilog
文件列表:
LICENSE (1072, 2017-05-05)
ahb_master (0, 2017-05-05)
ahb_master\bench (0, 2017-05-05)
ahb_master\bench\ahb_master_test.f (97, 2017-05-05)
ahb_master\bench\ahb_master_test.sv (4060, 2017-05-05)
ahb_master\bench\components (0, 2017-05-05)
ahb_master\bench\components\ahb_arbiter_sim.sv (1760, 2017-05-05)
ahb_master\bench\components\ahb_slave_sim.sv (3086, 2017-05-05)
ahb_master\scripts (0, 2017-05-05)
ahb_master\scripts\run_sim.csh (248, 2017-05-05)
ahb_master\scripts\source_it.csh (395, 2017-05-05)
ahb_master\sources (0, 2017-05-05)
ahb_master\sources\ahb_master.f (40, 2017-05-05)
ahb_master\sources\ahb_master.v (14887, 2017-05-05)
docs (0, 2017-05-05)
docs\amba.pdf (1916056, 2017-05-05)
# FreeAHB (Experimental)
Author: Revanth Kamaraj (revanth91kamaraj@gmail.com)
This repository currently provides an AHB 2.0 Master.
Icarus Verilog 10.0 or higher is required to simulate the design.
## Features of the AHB master:
- Bursts are done using a combination of INCR16/INCR8/INCR4 and INCR.
- Supports slaves with SPLIT/RETRY capability.
## To run simulations:
- Source the source\_it.csh file in scripts. Set the paths in the script correctly.
- Execute the run\_sim.csh file in scripts. A VVP file will be generated in the scratch folder. Execute it using vvp.
NOTE: If you define X\_INJECTION, the bench will run with data being made x when invalid (dav=0) to ensure
a more robust design test (x-injection). If you do not define X\_INJECTION, the bench will make data = 0
when data valid = 0. It is recommended that you use x injection when testing the design for a more robust
test.
## NOTE: While the master design is complete, it should be treated as very experimental in its current form.
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