ex2_seg7
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3686KB
下载次数：10
上传日期：2011-06-21 21:03:31
上 传 者：
fylfxj424
说明： 基于FPGA的七段数码管实验，怎样点亮数码管
(The seven-segment FPGA-based experiment, how light LED)
文件列表:
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.asm.qmsg (1980, 2009-05-21)
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.eda.qmsg (2275, 2009-05-21)
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.fit.qmsg (14048, 2009-05-21)
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.map.qmsg (3147, 2009-05-21)
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.qmsg (26095, 2009-05-21)
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.sta.qmsg (4416, 2009-05-21)
ex2_seg7\seg7_verilog\db\prev_cmp_seg7.tan.qmsg (20330, 2009-05-21)
ex2_seg7\seg7_verilog\db\seg7.(0).cnf.cdb (9533, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.(0).cnf.hdb (1923, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.asm.qmsg (1991, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cbx.xml (86, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.bpm (514, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.cdb (25275, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.ecobp (28, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.hdb (10576, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.kpt (335, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.logdb (4, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp.rdb (15088, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp0.ddb (35239, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.cmp_merge.kpt (341, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.db_info (137, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.eco.cdb (161, 2011-03-07)
ex2_seg7\seg7_verilog\db\seg7.eda.qmsg (2274, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.fit.qmsg (22314, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.hier_info (3474, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.hif (1714, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.lpc.html (430, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.lpc.rdb (385, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.lpc.txt (1060, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.bpm (500, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.cdb (7659, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.ecobp (28, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.hdb (9632, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.kpt (31423, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.logdb (4, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map.qmsg (3158, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map_bb.cdb (630, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map_bb.hdb (6527, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.map_bb.logdb (4, 2009-08-31)
ex2_seg7\seg7_verilog\db\seg7.pre_map.cdb (8979, 2009-08-31)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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