CPU-Design-Based-on-RISC-V
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：1452KB
下载次数：0
上传日期：2019-12-14 10:30:11
上 传 者：
sh-1993
说明： 使用Verilog编程语言和Vivado IDE进行开发。
(Development using Verilog programing language and Vivado IDE .)
文件列表:
project_demo (0, 2019-12-14)
project_demo\project_demo.cache (0, 2019-12-14)
project_demo\project_demo.cache\wt (0, 2019-12-14)
project_demo\project_demo.cache\wt\gui_handlers.wdf (10799, 2019-12-14)
project_demo\project_demo.cache\wt\java_command_handlers.wdf (2085, 2019-12-14)
project_demo\project_demo.cache\wt\project.wpc (59, 2019-12-14)
project_demo\project_demo.cache\wt\synthesis.wdf (5359, 2019-12-14)
project_demo\project_demo.cache\wt\synthesis_details.wdf (97, 2019-12-14)
project_demo\project_demo.cache\wt\webtalk_pa.xml (8931, 2019-12-14)
project_demo\project_demo.cache\wt\xsim.wdf (252, 2019-12-14)
project_demo\project_demo.hw (0, 2019-12-14)
project_demo\project_demo.hw\project_demo.lpr (284, 2019-12-14)
project_demo\project_demo.ip_user_files (0, 2019-12-14)
project_demo\project_demo.runs (0, 2019-12-14)
project_demo\project_demo.runs\.jobs (0, 2019-12-14)
project_demo\project_demo.runs\.jobs\vrs_config_1.xml (214, 2019-12-14)
project_demo\project_demo.runs\.jobs\vrs_config_2.xml (214, 2019-12-14)
project_demo\project_demo.runs\.jobs\vrs_config_3.xml (214, 2019-12-14)
project_demo\project_demo.runs\synth_1 (0, 2019-12-14)
project_demo\project_demo.runs\synth_1\.Vivado_Synthesis.queue.rst (0, 2019-12-14)
project_demo\project_demo.runs\synth_1\.vivado.begin.rst (175, 2019-12-14)
project_demo\project_demo.runs\synth_1\.vivado.end.rst (0, 2019-12-14)
project_demo\project_demo.runs\synth_1\ISEWrap.js (7306, 2019-12-14)
project_demo\project_demo.runs\synth_1\ISEWrap.sh (1623, 2019-12-14)
project_demo\project_demo.runs\synth_1\gen_run.xml (14024, 2019-12-14)
project_demo\project_demo.runs\synth_1\htr.txt (392, 2019-12-14)
project_demo\project_demo.runs\synth_1\project.wdf (3607, 2019-12-14)
project_demo\project_demo.runs\synth_1\rundef.js (1295, 2019-12-14)
project_demo\project_demo.runs\synth_1\runme.bat (219, 2019-12-14)
project_demo\project_demo.runs\synth_1\runme.log (18624, 2019-12-14)
project_demo\project_demo.runs\synth_1\runme.sh (1161, 2019-12-14)
project_demo\project_demo.runs\synth_1\test_alu_ctr.dcp (3125, 2019-12-14)
project_demo\project_demo.runs\synth_1\test_alu_ctr.tcl (5431, 2019-12-14)
project_demo\project_demo.runs\synth_1\test_alu_ctr.vds (18970, 2019-12-14)
project_demo\project_demo.runs\synth_1\test_alu_ctr_utilization_synth.pb (224, 2019-12-14)
project_demo\project_demo.runs\synth_1\test_alu_ctr_utilization_synth.rpt (7288, 2019-12-14)
project_demo\project_demo.runs\synth_1\vivado.jou (730, 2019-12-14)
... ...
# 注:
- 主文件为仿真文件 test_cpu_top.v ,运行该文件即可对整个 CPU 进行仿真;
- 可以直接将该项目导入 Vivado(不需要手动拷贝),具体方法自行上网了解;
- inst_rom.v 和 data_mem.v 中配置的 inst_rom.data 和 data_rom.data 的文件目录需要按照本机进行更改;
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