文件列表:

SPI_FullDuplex_ComDMA\EWARM\Project.ewd (45356, 2019-06-27)
SPI_FullDuplex_ComDMA\EWARM\Project.ewp (29712, 2019-06-27)
SPI_FullDuplex_ComDMA\EWARM\Project.eww (161, 2019-06-27)
SPI_FullDuplex_ComDMA\EWARM\startup_stm32h743xx.s (39112, 2019-06-27)
SPI_FullDuplex_ComDMA\EWARM\stm32h743xx_flash.icf (1598, 2019-06-27)
SPI_FullDuplex_ComDMA\Inc\main.h (3654, 2019-06-27)
SPI_FullDuplex_ComDMA\Inc\stm32h7xx_hal_conf.h (14359, 2019-06-27)
SPI_FullDuplex_ComDMA\Inc\stm32h7xx_it.h (1905, 2019-06-27)
SPI_FullDuplex_ComDMA\MDK-ARM\DebugConfig\STM32H743ZI-Nucleo_STM32H743ZITx_1.1.0.dbgconf (4196, 2019-06-07)
SPI_FullDuplex_ComDMA\MDK-ARM\Project.uvguix.idea (182119, 2019-12-17)
SPI_FullDuplex_ComDMA\MDK-ARM\Project.uvoptx (15457, 2019-12-02)
SPI_FullDuplex_ComDMA\MDK-ARM\Project.uvprojx (19199, 2019-11-25)
SPI_FullDuplex_ComDMA\MDK-ARM\RTE\_STM32H743ZI-Nucleo\RTE_Components.h (357, 2019-11-25)
SPI_FullDuplex_ComDMA\MDK-ARM\startup_stm32h743xx.s (44755, 2019-06-27)
SPI_FullDuplex_ComDMA\Src\main.c (12221, 2019-06-27)
SPI_FullDuplex_ComDMA\Src\stm32h7xx_hal_msp.c (7703, 2019-06-27)
SPI_FullDuplex_ComDMA\Src\stm32h7xx_it.c (4829, 2019-06-27)
SPI_FullDuplex_ComDMA\Src\system_stm32h7xx.c (11857, 2019-06-27)
SPI_FullDuplex_ComDMA\SW4STM32\startup_stm32h743xx.s (34977, 2019-06-27)
SPI_FullDuplex_ComDMA\SW4STM32\STM32H743ZI-Nucleo\.cproject (11992, 2019-06-27)
SPI_FullDuplex_ComDMA\SW4STM32\STM32H743ZI-Nucleo\.project (4202, 2019-06-27)
SPI_FullDuplex_ComDMA\SW4STM32\STM32H743ZI-Nucleo\STM32H743ZITx_FLASH.ld (4829, 2019-06-27)
SPI_FullDuplex_ComDMA\MDK-ARM\RTE\_STM32H743ZI-Nucleo (0, 2019-11-25)
SPI_FullDuplex_ComDMA\MDK-ARM\DebugConfig (0, 2019-11-25)
SPI_FullDuplex_ComDMA\MDK-ARM\RTE (0, 2019-11-25)
SPI_FullDuplex_ComDMA\MDK-ARM\STM32H743ZI-Nucleo (0, 2019-11-25)
SPI_FullDuplex_ComDMA\SW4STM32\STM32H743ZI-Nucleo (0, 2019-06-27)
SPI_FullDuplex_ComDMA\EWARM (0, 2019-06-27)
SPI_FullDuplex_ComDMA\Inc (0, 2019-06-27)
SPI_FullDuplex_ComDMA\MDK-ARM (0, 2019-12-17)
SPI_FullDuplex_ComDMA\Src (0, 2019-06-27)
SPI_FullDuplex_ComDMA\SW4STM32 (0, 2019-06-27)
SPI_FullDuplex_ComDMA (0, 2019-06-27)

/** @page SPI_FullDuplex_ComDMA SPI Full Duplex DMA example @verbatim ******************** (C) COPYRIGHT 2017 STMicroelectronics ******************* * @file SPI/SPI_FullDuplex_ComDMA/readme.txt * @author MCD Application Team * @brief Description of the SPI Full Duplex DMA example. ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** @endverbatim @par Example Description This example shows how to perform SPI data buffer transmission/reception between two boards via DMA. _________________________ _________________________ | ______________| |__________________ | | | SPI1 | | SPI1 | | | | | | | | | | CLK(PA5)|______________________|(PA5)CLK CN7.D13 | | | | | | | | | | MISO(PA6)|______________________|(PA6)MISO CN7.D12 | | | | | | | | | | MOSI(PA7)|______________________|(PA7)MOSI CN7.D11 | | | | | | | | | |______________| |__________________| | | __ | | | | |__| | | | | USER | | | | GND|______________________|GND | | | | | |_STM32H7 Master _________| |_STM32H7 Slave __________| @note The connection between the pins should use a short wires and a common Ground. HAL architecture allows user to easily change code to move to Polling or IT mode. To see others communication modes please check following examples: SPI\SPI_FullDuplex_ComPolling SPI\SPI_FullDuplex_ComIT At the beginning of the main program the HAL_Init() function is called to reset all the peripherals, initialize the Flash interface and the systick. The SystemClock_Config() function is used to configure the system clock for STM32H743xx Devices : The CPU at 400MHz The HCLK for D1 Domain AXI and AHB3 peripherals , D2 Domain AHB1/AHB2 peripherals and D3 Domain AHB4 peripherals at 200MHz. The APB clock dividers for D1 Domain APB3 peripherals, D2 Domain APB1 and APB2 peripherals and D3 Domain APB4 peripherals to run at 100MHz. The SPI peripheral configuration is ensured by the HAL_SPI_Init() function. This later is calling the HAL_SPI_MspInit()function which core is implementing the configuration of the needed SPI resources according to the used hardware (CLOCK, GPIO, DMA and NVIC). You may update this function to change SPI configuration. The SPI communication is then initiated. The HAL_SPI_TransmitReceive_DMA() function allows the reception and the transmission of a predefined data buffer at the same time (Full Duplex Mode). The user can choose between Master and Slave through "#define MASTER_BOARD" in the "main.c" file. If the Master board is used, the "#define MASTER_BOARD" must be uncommented. If the Slave board is used the "#define MASTER_BOARD" must be commented. For this example the aTxBuffer is predefined and the aRxBuffer size is same as aTxBuffer. In a first step after the user press the User push-button, SPI Master starts the communication by sending aTxBuffer and receiving aRxBuffer through HAL_SPI_TransmitReceive_DMA(), at the same time SPI Slave transmits aTxBuffer and receives aRxBuffer through HAL_SPI_TransmitReceive_DMA(). The callback functions (HAL_SPI_TxRxCpltCallback and HAL_SPI_ErrorCallbackand) update the variable wTransferState used in the main function to check the transfer status. Finally, aRxBuffer and aTxBuffer are compared through Buffercmp() in order to check buffers correctness. STM32 board's LEDs can be used to monitor the transfer status: - LED1 toggles quickly on master board waiting User push-button to be pressed. - LED1 turns ON when the transmission process is complete. - LED2 turns ON when the reception process is complete. - LED3 turns ON when there is an error in transmission/reception process. @note SPIx instance used and associated resources can be updated in "main.h" file depending hardware configuration used. @note You need to perform a reset on Slave board, then perform it on Master board to have the correct behaviour of this example. @note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds) based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function. @note The example need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation. @note It is highly recommanded to set the SPI parameter "MasterKeepIOState" to "SPI_MASTER_KEEP_IO_STATE_ENABLE" at init time. This configuration allows to avoid glitches on SPI lines especially the clock. Glitches that could lead to Master/Slave desynchronization. This config allows SPI Master to keep control on output state even if it is disabled. @Note If the application is using the DTCM/ITCM memories (@0x20000000/ 0x0000000: not cacheable and only accessible by the Cortex M7 and the MDMA), no need for cache maintenance when the Cortex M7 and the MDMA access these RAMs. If the application needs to use DMA(or other masters) based access or requires more RAM, then the user has to: - Use a non TCM SRAM. (example : D1 AXI-SRAM @ 0x24000000) - Add a cache maintenance mechanism to ensure the cache coherence between CPU and other masters(DMAs,DMA2D,LTDC,MDMA). - The addresses and the size of cacheable buffers (shared between CPU and other masters) must be properlydefined to be aligned to L1-CACHE line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence. Depending on the use case it is also possible to configure the cache attributes using the MPU. Please refer to the AN4838 "Managing memory protection unit (MPU) in STM32 MCUs" Please refer to the AN4839 "Level 1 cache on STM32F7 Series" @par Directory contents - SPI/SPI_FullDuplex_ComDMA/Inc/stm32h7xx_hal_conf.h HAL configuration file - SPI/SPI_FullDuplex_ComDMA/Inc/stm32h7xx_it.h Interrupt handlers header file - SPI/SPI_FullDuplex_ComDMA/Inc/main.h Header for main.c module - SPI/SPI_FullDuplex_ComDMA/Src/stm32h7xx_it.c Interrupt handlers - SPI/SPI_FullDuplex_ComDMA/Src/main.c Main program - SPI/SPI_FullDuplex_ComDMA/Src/system_stm32h7xx.c stm32h7xx system source file - SPI/SPI_FullDuplex_ComDMA/Src/stm32h7xx_hal_msp.c HAL MSP file @par Hardware and Software environment - This example runs on STM32H743xx devices. - This example has been tested with NUCLEO-H743ZI board and can be easily tailored to any other supported device and development board. - NUCLEO-H743ZI Set-up - Connect Master board PA5 to Slave Board PA5 - Connect Master board PA6 to Slave Board PA6 - Connect Master board PA7 to Slave Board PA7 - Connect Master board GND to Slave Board GND @par How to use it ? In order to make the program work, you must do the following: - Open your preferred toolchain - Rebuild all files and load your image into target memory o Uncomment "#define MASTER_BOARD" and load the project in Master Board o Comment "#define MASTER_BOARD" and load the project in Slave Board - Run the example *

© COPYRIGHT STMicroelectronics

*/

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