virtex7_pcie_dma_2019-08-20
所属分类：其他
开发工具：VHDL
文件大小：9995KB
下载次数：7
上传日期：2019-12-25 16:25:21
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诡迹xjn
说明： Direct Memory Access (DMA) interface for the Xilinx Virtex-7 PCIe Gen3 hard block. The core is not meant to be flexible among different architectures, but especially designed for the 256 bit wide AXI4-Stream interface of the Xilinx Virtex-7 and Ultrascale FPGA Gen3 Integrated Block for PCI Express (PCIe) 2019-08-20刚更新的最新版本 v3.0
(Direct Memory Access (DMA) interface for the Xilinx Virtex-7 PCIe Gen3 hard block. The core is not meant to be flexible among different architectures, but especially designed for the 256 bit wide AXI4-Stream interface of the Xilinx Virtex-7 and Ultrascale FPGA Gen3 Integrated Block for PCI Express (PCIe))
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virtex7_pcie_dma_2019-08-20 (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\branches (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\tags (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\benchmark.tex (1652, 2016-11-23)
virtex7_pcie_dma_2019-08-20\trunk\documentation\bibliography.tex (6185, 2019-05-17)
virtex7_pcie_dma_2019-08-20\trunk\documentation\customizing.tex (3361, 2017-10-24)
virtex7_pcie_dma_2019-08-20\trunk\documentation\design.tex (15777, 2019-05-17)
virtex7_pcie_dma_2019-08-20\trunk\documentation\doxygen (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\doxygen\mainpage.dox (8530, 2015-01-09)
virtex7_pcie_dma_2019-08-20\trunk\documentation\doxygen\pcie_dma_core.doxyfile (99573, 2015-01-09)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template\pictures (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template\pictures\footer.png (42496, 2015-01-09)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template\pictures\NIKHEF.pdf (2970, 2015-01-09)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template\pictures\NIKHEF.png (7065, 2015-01-09)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template\template.tex (3676, 2019-05-17)
virtex7_pcie_dma_2019-08-20\trunk\documentation\et_template\titlepage.tex (189, 2015-01-09)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application.tex (4632, 2016-11-23)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\appendix.tex (5175, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\conclusion.tex (1404, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\et_template (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\et_template\pictures (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\et_template\pictures\footer.png (42496, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\et_template\pictures\NIKHEF.pdf (2970, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\et_template\template.tex (3650, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\et_template\titlepage.tex (189, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures (0, 2019-08-20)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures\benchmark_application.pdf (36213, 2017-10-24)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures\blocksize_plot.pdf (4897, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures\dma_core_structure.png (165412, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures\fifos_full.pdf (86556, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures\fifo_full_inverted.png (43013, 2016-01-29)
virtex7_pcie_dma_2019-08-20\trunk\documentation\example_application\figures\full_application_structure.pdf (20645, 2016-01-29)
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## Block Diagram
## Description
Wupper is designed by [Nikhef](http://www.nikhef.nl) (Amsterdam, The Netherlands) for the CERN [ATLAS](http://atlas.cern) / [FELIX](https://atlas-project-felix.web.cern.ch/atlas-project-felix) project.
Its main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block.
Wupper is specifically designed for the 256 bit wide AXI4-Stream interface of the [Xilinx Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)](https://www.xilinx.com/products/intellectual-property/7_series_gen_3_pci_express.html).
Wupper has been also successfully ported to Xilinx Kintex UltraScale FPGAs.
#### DMA read and write
The main purpose of Wupper is therefore to provide an interface to standard FIFOs.
This is the done by the _DMA\_read\_write_ block in the diagram above.
The read/write FIFOs have the same width as the Xilinx AXI4-Stream interface (256 bits) and run at 250 MHz.
The application side of the FPGA design can simply read or write the FIFOs.
Wupper will handle the transfer to Host PC memory, according to the addresses specified in the _DMA descriptors_.
#### DMA control
Another functionality of Wupper is thus to manage a set of DMA descriptors.
Descriptors consist of an address, a read/write flag, the transfer size (number of 32 bit words) and an enable line.
Descriptors are handled by the _DMA\_control_ block.
These descriptors are mapped as normal PCIe memory or IO registers.
Besides the descriptors and the enable line (one per descriptor), a status register for every descriptor is provided in the register map.
#### Generic register map
Besides DMA specific functions, the DMA control block can also handle generic _control_ and _monitor_ registers for user application.
#### Interrupt handler
Wupper is provided with a generic MSI-X compatible interrupt controller.
#### Implementation info
For synthesis and implementation of the cores, it is recommend to use Xilinx Vivado 2014.2.
Other IP cores (FIFO, clock wizard and PCIe) are provided in the Xilinx .xci format, as well as the constraints file (.xdc) is in the Vivado 2014.2 Format.
Wupper is also known to work well with Vivado 2014.4, constraints will be updated.
For portability reasons, no Xilinx project files will be supplied with Wupper.
Instead, a bundle of _TCL scripts_ has been supplied to create a project and import all necessary files, as well as to do the synthesis and implementation.
These scripts are be described in details in the [/documentation/wupper.pdf](http://opencores.org/websvn,filedetails?repname=virtex7_pcie_dma&path=%2Fvirtex7_pcie_dma%2Ftrunk%2Fdocumentation%2Fwupper.pdf) distributed with Wupper.
## Feedback
\>> Give comments and feedback using the official core thread on the OpenCores forum:
[forum\_thread](http://opencores.org/forum,Cores,0,5580)
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