aes_core
所属分类：加密解密
开发工具：MultiPlatform
文件大小：78KB
下载次数：631
上传日期：2006-03-21 22:31:47
上 传 者：
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说明： AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。
(AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.)
文件列表:
aes_core\vim_session.vim (5465, 2002-11-09)
aes_core\bench\CVS\Entries (14, 2004-03-14)
aes_core\bench\CVS\Repository (15, 2004-03-14)
aes_core\bench\CVS\Root (14, 2004-03-14)
aes_core\bench\CVS (0, 2005-04-28)
aes_core\bench\verilog\test_bench_top.v (37033, 2002-11-13)
aes_core\bench\verilog\CVS\Entries (51, 2004-03-14)
aes_core\bench\verilog\CVS\Repository (23, 2004-03-14)
aes_core\bench\verilog\CVS\Root (14, 2004-03-14)
aes_core\bench\verilog\CVS (0, 2005-04-28)
aes_core\bench\verilog (0, 2005-04-28)
aes_core\bench (0, 2005-04-28)
aes_core\CVS\Entries (104, 2004-03-14)
aes_core\CVS\Repository (9, 2004-03-14)
aes_core\CVS\Root (14, 2004-03-14)
aes_core\CVS (0, 2005-04-28)
aes_core\doc\aes.pdf (73346, 2002-11-13)
aes_core\doc\CVS\Entries (45, 2004-03-14)
aes_core\doc\CVS\Repository (13, 2004-03-14)
aes_core\doc\CVS\Root (14, 2004-03-14)
aes_core\doc\CVS (0, 2005-04-28)
aes_core\doc (0, 2005-04-28)
aes_core\rtl\CVS\Entries (14, 2004-03-14)
aes_core\rtl\CVS\Repository (13, 2004-03-14)
aes_core\rtl\CVS\Root (14, 2004-03-14)
aes_core\rtl\CVS (0, 2005-04-28)
aes_core\rtl\verilog\aes_cipher_top.v (10230, 2002-11-09)
aes_core\rtl\verilog\aes_inv_cipher_top.v (11671, 2002-11-09)
aes_core\rtl\verilog\aes_inv_sbox.v (8257, 2002-11-09)
aes_core\rtl\verilog\aes_key_expand_128.v (3914, 2002-11-09)
aes_core\rtl\verilog\aes_rcon.v (3773, 2002-11-09)
aes_core\rtl\verilog\aes_sbox.v (8246, 2002-11-09)
aes_core\rtl\verilog\timescale.v (22, 2002-11-13)
aes_core\rtl\verilog\CVS\Entries (358, 2004-03-14)
aes_core\rtl\verilog\CVS\Repository (21, 2004-03-14)
aes_core\rtl\verilog\CVS\Root (14, 2004-03-14)
aes_core\rtl\verilog\CVS (0, 2005-04-28)
aes_core\rtl\verilog (0, 2005-04-28)
aes_core\rtl (0, 2005-04-28)
aes_core\sim\CVS\Entries (14, 2004-03-14)
... ...
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