generic_fifos
所属分类：VHDL/FPGA/Verilog
开发工具：MultiPlatform
文件大小：26KB
下载次数：31
上传日期：2006-03-21 23:23:26
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说明： 用HDL语言编写的通用fifo源码，通过对fifo的宽度和深度进行配置，可以产生我们所需要的fifo，还包括fifo的测试程序和仿真Makefile脚本
(with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulation scripts Makefile)
文件列表:
generic_fifos\bench\CVS\Entries (14, 2004-03-14)
generic_fifos\bench\CVS\Repository (20, 2004-03-14)
generic_fifos\bench\CVS\Root (14, 2004-03-14)
generic_fifos\bench\CVS (0, 2005-04-28)
generic_fifos\bench\verilog\test_bench_top.v (11112, 2002-09-25)
generic_fifos\bench\verilog\CVS\Entries (55, 2004-03-14)
generic_fifos\bench\verilog\CVS\Repository (28, 2004-03-14)
generic_fifos\bench\verilog\CVS\Root (14, 2004-03-14)
generic_fifos\bench\verilog\CVS (0, 2005-04-28)
generic_fifos\bench\verilog (0, 2005-04-28)
generic_fifos\bench (0, 2005-04-28)
generic_fifos\CVS\Entries (42, 2004-03-14)
generic_fifos\CVS\Repository (14, 2004-03-14)
generic_fifos\CVS\Root (14, 2004-03-14)
generic_fifos\CVS (0, 2005-04-28)
generic_fifos\doc\CVS\Entries (49, 2004-03-14)
generic_fifos\doc\CVS\Repository (18, 2004-03-14)
generic_fifos\doc\CVS\Root (14, 2004-03-14)
generic_fifos\doc\CVS (0, 2005-04-28)
generic_fifos\doc (0, 2005-04-28)
generic_fifos\rtl\CVS\Entries (14, 2004-03-14)
generic_fifos\rtl\CVS\Repository (18, 2004-03-14)
generic_fifos\rtl\CVS\Root (14, 2004-03-14)
generic_fifos\rtl\CVS (0, 2005-04-28)
generic_fifos\rtl\verilog\generic_fifo_dc.v (8174, 2002-09-25)
generic_fifos\rtl\verilog\generic_fifo_dc_gray.v (9523, 2004-01-13)
generic_fifos\rtl\verilog\generic_fifo_lfsr.v (7450, 2002-10-30)
generic_fifos\rtl\verilog\generic_fifo_sc_a.v (10097, 2002-09-25)
generic_fifos\rtl\verilog\generic_fifo_sc_b.v (9040, 2002-09-25)
generic_fifos\rtl\verilog\lfsr.v (4032, 2002-10-30)
generic_fifos\rtl\verilog\timescale.v (23, 2002-09-25)
generic_fifos\rtl\verilog\CVS\Entries (362, 2004-03-14)
generic_fifos\rtl\verilog\CVS\Repository (26, 2004-03-14)
generic_fifos\rtl\verilog\CVS\Root (14, 2004-03-14)
generic_fifos\rtl\verilog\CVS (0, 2005-04-28)
generic_fifos\rtl\verilog (0, 2005-04-28)
generic_fifos\rtl (0, 2005-04-28)
generic_fifos\sim\CVS\Entries (14, 2004-03-14)
generic_fifos\sim\CVS\Repository (18, 2004-03-14)
... ...
Generic FIFOs
=============
Status
------
All FIFOs that are release are done. They have been simulated
and most of them have been used in one way or another in one
of my projects. Some have been verified in real hardware.
There probably will be several more flavors of FIFOs released
in the future.
Test Bench
----------
I have included a very basic test bench. It should be viewed
as a starting point to write a more comprehensive and complete
test bench.
Documentation
-------------
There is nothing beyond this README file and the headers in
each of the modules. I hope that information will be sufficient.
This first release has 3 different FIFOs:
- generic_fifo_sc_a.v
- generic_fifo_sc_b.v
- generic_fifo_dc.v
The first two (generic_fifo_sc_a.v and generic_fifo_sc_b.v)
are essentially equivalent functionality wise. Some internal
are different implemented between the two. Both are single
clock FIFOs (sc), with same input port and output port widths.
The third FIFO, is a dual clock fifo. Read and Write ports have
independent clocks. Otherwise it is similar in functionality
to the single clock FIFOs.
FIFO depth and width are parameterized.
Again, check the headers of each of the FIFOs for more information.
Misc
----
The Generic FIFOs Project Page is:
http://www.opencores.org/cores/generic_fifos/
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
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