hdmi_out
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：1963KB
下载次数：5
上传日期：2020-02-10 09:49:11
上 传 者：
flyingLee
说明： 软核实现HMDI视频流编解码，支持多路输出复用和AXI总线
(The soft core realizes hmdi video stream encoding and decoding, supports multiplex output and Axi bus)
文件列表:
.Xil (0, 2019-12-04)
.Xil\Vivado-12400-DESKTOP-AJKA516 (0, 2019-12-04)
.Xil\Vivado-12400-DESKTOP-AJKA516\wave (0, 2019-12-04)
.Xil\Vivado-12736-DESKTOP-AJKA516 (0, 2019-12-04)
.Xil\Vivado-12736-DESKTOP-AJKA516\wave (0, 2019-12-04)
.Xil\Vivado-12860-DESKTOP-AJKA516 (0, 2019-12-04)
.Xil\Vivado-12860-DESKTOP-AJKA516\wave (0, 2019-12-04)
.Xil\Vivado-5880-DESKTOP-AJKA516 (0, 2019-12-04)
.Xil\Vivado-5880-DESKTOP-AJKA516\wave (0, 2019-12-04)
.Xil\Vivado-7608-DESKTOP-AJKA516 (0, 2019-12-04)
.Xil\Vivado-7608-DESKTOP-AJKA516\wave (0, 2019-12-04)
hdmi_out_test.cache (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\activehdl (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\ies (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\modelsim (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\questa (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\riviera (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\vcs (0, 2019-12-04)
hdmi_out_test.cache\compile_simlib\xcelium (0, 2019-12-04)
hdmi_out_test.cache\ip (0, 2019-12-04)
hdmi_out_test.cache\ip\2017.4 (0, 2019-12-04)
hdmi_out_test.cache\wt (0, 2019-12-04)
hdmi_out_test.cache\wt\project.wpc (61, 2019-12-04)
hdmi_out_test.hw (0, 2019-12-04)
hdmi_out_test.hw\hdmi_out_test.lpr (343, 2019-12-04)
hdmi_out_test.hw\hw_1 (0, 2019-12-04)
hdmi_out_test.hw\hw_1\hw.xml (824, 2019-12-04)
hdmi_out_test.hw\hw_1\wave (0, 2019-12-04)
hdmi_out_test.ip_user_files (0, 2019-12-04)
hdmi_out_test.ip_user_files\ip (0, 2019-12-04)
hdmi_out_test.ip_user_files\ip\rgb2dvi_0 (0, 2019-12-04)
hdmi_out_test.ip_user_files\ip\rgb2dvi_0\rgb2dvi_0.veo (3338, 2019-12-04)
hdmi_out_test.ip_user_files\ip\rgb2dvi_0\rgb2dvi_0.vho (3609, 2019-12-04)
hdmi_out_test.ip_user_files\ip\rgb2dvi_0\rgb2dvi_0_stub.v (1673, 2019-12-04)
hdmi_out_test.ip_user_files\ip\rgb2dvi_0\rgb2dvi_0_stub.vhdl (1747, 2019-12-04)
hdmi_out_test.ip_user_files\ip\video_clock (0, 2019-12-04)
hdmi_out_test.ip_user_files\ip\video_clock\video_clock.veo (3760, 2019-12-04)
hdmi_out_test.ip_user_files\ip\video_clock\video_clock_stub.v (1287, 2019-12-04)
hdmi_out_test.ip_user_files\ip\video_clock\video_clock_stub.vhdl (1264, 2019-12-04)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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