AC6102_UART_TFT43_IMG
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2099KB
下载次数：0
上传日期：2020-02-12 10:44:10
上 传 者：
gaoshanlioushui
说明： XILINX公司FPGA采用vhdl语言进行串口通信
(FPGA uses VHDL language for serial communication)
文件列表:
AC6102_UART_TFT43_IMG\DDR2_phy_autodetectedpins.tcl (1163, 2019-03-07)
AC6102_UART_TFT43_IMG\DDR2_phy_summary.csv (1121, 2019-03-07)
AC6102_UART_TFT43_IMG\ip_core\pll.ppf (353, 2017-01-28)
AC6102_UART_TFT43_IMG\ip_core\pll.qip (351, 2017-01-28)
AC6102_UART_TFT43_IMG\ip_core\pll.v (14582, 2017-01-28)
AC6102_UART_TFT43_IMG\ip_core\pll_bb.v (10798, 2017-01-28)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.asm.rpt (7563, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.done (26, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.eda.rpt (8926, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.fit.rpt (1488279, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.fit.smsg (703, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.fit.summary (650, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.flow.rpt (17943, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.jdi (236, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.map.rpt (5480767, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.map.smsg (20815, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.map.summary (504, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.pin (58610, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.sof (1171634, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.sta.rpt (54434025, 2019-03-07)
AC6102_UART_TFT43_IMG\output_files\UART_DDR2_TFT_IMG.sta.summary (46738, 2019-03-07)
AC6102_UART_TFT43_IMG\pll.qip (0, 2017-01-01)
AC6102_UART_TFT43_IMG\PLLJ_PLLSPE_INFO.txt (460, 2019-03-07)
AC6102_UART_TFT43_IMG\RemoveTemp.bat (246, 2016-01-19)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\altmemphy-library\auk_ddr_hp_controller.ocp (488, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_addr_cmd.v (24623, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_addr_cmd_wrap.v (55196, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_arbiter.v (52523, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_buffer.v (4029, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_buffer_manager.v (7962, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_burst_gen.v (68287, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_burst_tracking.v (3799, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_cmd_gen.v (120771, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_controller.v (176407, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_controller_st_top.v (96011, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_csr.v (51657, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_dataid_manager.v (37178, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_ddr2_odt_gen.v (18004, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_ddr3_odt_gen.v (17824, 2016-12-07)
AC6102_UART_TFT43_IMG\rtl\DDR2_Control_4Port\DDR2\alt_mem_ddrx_define.iv (1402, 2016-12-07)
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