fpga_fifo-master
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：12KB
下载次数：3
上传日期：2020-03-06 15:33:05
上 传 者：
6771883
说明： fifo源代码，深度可以任意设置，内含fifo的ip核等
(FIFO source code, depth can be set arbitrarily, including FIFO IP core, etc)
文件列表:
doc (0, 2018-03-20)
doc\diagrams (0, 2018-03-20)
doc\diagrams\read-4-from-fifo-3.js (582, 2018-03-20)
dual_port_mem (0, 2018-03-20)
dual_port_mem\dual_port_mem.vhd (1606, 2018-03-20)
dual_port_mem\dual_port_mem_tb.vhd (3777, 2018-03-20)
fifo (0, 2018-03-20)
fifo\fifo.vhd (4740, 2018-03-20)
fifo\fifo_tb.vhd (10518, 2018-03-20)
ptr_sync (0, 2018-03-20)
ptr_sync\ptr_sync.vhd (1077, 2018-03-20)
ptr_sync\ptr_sync_tb.vhd (2175, 2018-03-20)
rd_ctrl (0, 2018-03-20)
rd_ctrl\rd_ctrl.vhd (3495, 2018-03-20)
rd_ctrl\rd_ctrl_tb.vhd (2613, 2018-03-20)
wr_ctrl (0, 2018-03-20)
wr_ctrl\wr_ctrl.vhd (3657, 2018-03-20)
wr_ctrl\wr_ctrl_tb.vhd (3798, 2018-03-20)
FPGA FIFO
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VHDL implementation of an asynchronous FIFO for FPGAs.
Based off a Verilog design by Clifford E. Cummings.
[http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf]
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