说明：  The MAX II CPLD has the following features: ■ Low-cost, low-power CPLD ■ Instant-on, non-volatile architecture ■ Standby current as low as 29 μA ■ Provides fast propagation delay and clock-to-output times ■ Provides four global clocks with two clocks available per logic array block (LAB) ■ UFM block up to 8 Kbits for non-volatile storage ■ MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V ■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
(The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-μm, 6-layermetal- flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.)