FIFO
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：252KB
下载次数：0
上传日期：2020-04-14 22:13:01
上 传 者：
hayto
说明： 包含同步异步FIFO的veilog代码描述，包含注释适合学习
(A description of the veilog code containing synchronous and asynchronous FIFO, with comments suitable for learning)
文件列表:
afifo_design (0, 2010-07-24)
afifo_design\sim (0, 2010-08-18)
afifo_design\sim\do.do (302, 2010-03-17)
afifo_design\sim\transcript (1296, 2010-08-18)
afifo_design\sim\vsim.wlf (32768, 2010-03-17)
afifo_design\sim\work (0, 2010-07-24)
afifo_design\sim\work\@afifo (0, 2010-07-24)
afifo_design\sim\work\@afifo\_primary.dat (1796, 2010-03-17)
afifo_design\sim\work\@afifo\_primary.dbs (5442, 2010-03-17)
afifo_design\sim\work\@afifo\_primary.vhd (716, 2010-03-17)
afifo_design\sim\work\@afifo\verilog.asm (14992, 2010-03-17)
afifo_design\sim\work\@afifo\verilog.rw (3857, 2010-03-17)
afifo_design\sim\work\@afifo_mem (0, 2010-07-24)
afifo_design\sim\work\@afifo_mem\_primary.dat (1570, 2010-03-17)
afifo_design\sim\work\@afifo_mem\_primary.dbs (3987, 2010-03-17)
afifo_design\sim\work\@afifo_mem\_primary.vhd (652, 2010-03-17)
afifo_design\sim\work\@afifo_mem\verilog.asm (21576, 2010-03-17)
afifo_design\sim\work\@afifo_mem\verilog.rw (4470, 2010-03-17)
afifo_design\sim\work\@afifo_rptr_empty (0, 2010-07-24)
afifo_design\sim\work\@afifo_rptr_empty\_primary.dat (752, 2010-03-17)
afifo_design\sim\work\@afifo_rptr_empty\_primary.dbs (2278, 2010-03-17)
afifo_design\sim\work\@afifo_rptr_empty\_primary.vhd (480, 2010-03-17)
afifo_design\sim\work\@afifo_rptr_empty\verilog.asm (13344, 2010-03-17)
afifo_design\sim\work\@afifo_rptr_empty\verilog.rw (2531, 2010-03-17)
afifo_design\sim\work\@afifo_sync_r2w (0, 2010-07-24)
afifo_design\sim\work\@afifo_sync_r2w\_primary.dat (869, 2010-03-17)
afifo_design\sim\work\@afifo_sync_r2w\_primary.dbs (2278, 2010-03-17)
afifo_design\sim\work\@afifo_sync_r2w\_primary.vhd (476, 2010-03-17)
afifo_design\sim\work\@afifo_sync_r2w\verilog.asm (9120, 2010-03-17)
afifo_design\sim\work\@afifo_sync_r2w\verilog.rw (2590, 2010-03-17)
afifo_design\sim\work\@afifo_sync_w2r (0, 2010-07-24)
afifo_design\sim\work\@afifo_sync_w2r\_primary.dat (869, 2010-03-17)
afifo_design\sim\work\@afifo_sync_w2r\_primary.dbs (2278, 2010-03-17)
afifo_design\sim\work\@afifo_sync_w2r\_primary.vhd (476, 2010-03-17)
afifo_design\sim\work\@afifo_sync_w2r\verilog.asm (9128, 2010-03-17)
afifo_design\sim\work\@afifo_sync_w2r\verilog.rw (2598, 2010-03-17)
afifo_design\sim\work\@afifo_wptr_full (0, 2010-07-24)
afifo_design\sim\work\@afifo_wptr_full\_primary.dat (749, 2010-03-17)
afifo_design\sim\work\@afifo_wptr_full\_primary.dbs (2240, 2010-03-17)
afifo_design\sim\work\@afifo_wptr_full\_primary.vhd (478, 2010-03-17)
... ...
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