aclock
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：3780KB
下载次数：0
上传日期：2020-04-17 17:29:10
上 传 者：
6710290
说明： 该实验程序分为若干个模块：分频模块，时分秒计数模块、译码显示模块、去抖模块、宽脉冲变窄脉冲模块、门电路“或”逻辑模块。
关键模块说明：
分频模块：将50MHz频率分频实现1HZ,作为时分秒模块计数时钟端；将50MHz频率分频实现1KHz,作为数码管刷新时钟频率。
去抖模块：通常按键的按下和抬起，键盘回路中会产生短暂的冲激信号，抖动的时间长短由按键的而机械特性决定的，一般为5ms-10ms。因此，通过双D触发器构成单稳态电路实现消抖。
宽脉冲变窄脉冲模块框图：D触发器输出端取反与触发器的输入相“与”,可以将宽脉冲变成窄脉冲。
(The experimental program is divided into several modules: frequency division module, hour, minute and second counting module, decoding display module, debounce module, wide pulse narrow pulse module, gate OR logic module.Key module description: Frequency division module: divide 50MHz frequency to achieve 1HZ, as the time-of-minute module count clock terminal; divide 50MHz frequency to achieve 1KHz, as the digital tube refresh clock frequency.)
文件列表:
aclock\aclock.qpf (1323, 2019-11-18)
aclock\aclock.qsf (5122, 2019-12-05)
aclock\aclock.qws (626, 2020-01-07)
aclock\aclock.vhd (3168, 2019-12-03)
aclock\aclock.vhd.bak (3779, 2019-11-18)
aclock\aclock_assignment_defaults.qdf (56018, 2019-11-30)
aclock\clock_narrow.vhd (343, 2019-11-29)
aclock\db\.cmp.kpt (205, 2019-12-05)
aclock\db\aclock.(0).cnf.cdb (2854, 2019-12-03)
aclock\db\aclock.(0).cnf.hdb (1753, 2019-12-03)
aclock\db\aclock.(1).cnf.cdb (4562, 2019-12-03)
aclock\db\aclock.(1).cnf.hdb (1195, 2019-12-03)
aclock\db\aclock.(2).cnf.cdb (2882, 2019-12-01)
aclock\db\aclock.(2).cnf.hdb (1466, 2019-12-01)
aclock\db\aclock.(3).cnf.cdb (989, 2019-12-01)
aclock\db\aclock.(3).cnf.hdb (666, 2019-12-01)
aclock\db\aclock.(4).cnf.cdb (2881, 2019-12-01)
aclock\db\aclock.(4).cnf.hdb (1460, 2019-12-01)
aclock\db\aclock.(5).cnf.cdb (2917, 2019-12-01)
aclock\db\aclock.(5).cnf.hdb (1429, 2019-12-01)
aclock\db\aclock.(6).cnf.cdb (4336, 2019-12-03)
aclock\db\aclock.(6).cnf.hdb (2592, 2019-12-03)
aclock\db\aclock.(7).cnf.cdb (2549, 2019-12-01)
aclock\db\aclock.(7).cnf.hdb (1089, 2019-12-01)
aclock\db\aclock.(8).cnf.cdb (817, 2019-12-01)
aclock\db\aclock.(8).cnf.hdb (619, 2019-12-01)
aclock\db\aclock.asm.qmsg (3032, 2019-12-05)
aclock\db\aclock.asm.rdb (864, 2019-12-05)
aclock\db\aclock.asm_labs.ddb (14777, 2019-12-05)
aclock\db\aclock.cbx.xml (88, 2019-12-05)
aclock\db\aclock.cmp.bpm (776, 2019-12-05)
aclock\db\aclock.cmp.cdb (54663, 2019-12-05)
aclock\db\aclock.cmp.hdb (20835, 2019-12-05)
aclock\db\aclock.cmp.idb (3141, 2019-12-05)
aclock\db\aclock.cmp.logdb (12991, 2019-12-05)
aclock\db\aclock.cmp.rdb (24936, 2019-12-05)
aclock\db\aclock.cmp_merge.kpt (209, 2019-12-05)
aclock\db\aclock.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd (746177, 2019-12-05)
aclock\db\aclock.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd (739560, 2019-12-05)
aclock\db\aclock.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd (740720, 2019-12-05)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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