文件列表:

Xilinx_AXI\hdl\verilog\axi_lite_master.v (33415, 2013-05-29)
Xilinx_AXI\hdl\verilog\axi_lite_slave.v (22985, 2013-05-29)
Xilinx_AXI\hdl\verilog\axi_master.v (31609, 2013-05-29)
Xilinx_AXI\hdl\verilog\axi_slave.v (24710, 2013-05-29)
Xilinx_AXI\hdl\verilog\axi_stream_master.v (7284, 2013-05-29)
Xilinx_AXI\hdl\verilog\axi_stream_slave.v (5921, 2013-05-29)
Xilinx_AXI\ip_repo_complete\vv_index.xml (6203, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\component.xml (28258, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\verilog\axi_lite_master.v (33415, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\xgui\axi_lite_master_v1_0.tcl (892, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0.zip (10190, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\component.xml (24457, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\verilog\axi_lite_slave.v (22985, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\xgui\axi_lite_slave_v1_0.tcl (247, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0.zip (7441, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\component.xml (38074, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\verilog\axi_master.v (31609, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0\xgui\axi_master_v1_0.tcl (2117, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_master_1.0.zip (11209, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\component.xml (38903, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\verilog\axi_slave.v (24710, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0\xgui\axi_slave_v1_0.tcl (1518, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_slave_1.0.zip (9250, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\component.xml (14530, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\verilog\axi_stream_master.v (7284, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0\xgui\axi_stream_master_v1_0.tcl (1563, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_master_1.0.zip (5414, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\component.xml (13864, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\verilog\axi_stream_slave.v (5921, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0\xgui\axi_stream_slave_v1_0.tcl (946, 2005-06-25)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_stream_slave_1.0.zip (4955, 2013-05-29)
Xilinx_AXI\source.tcl (18373, 2013-05-29)
Xilinx_AXI\tb\verilog\axi_stream_system_wrapper_tb.v (2781, 2013-05-29)
Xilinx_AXI\tb\verilog\axi_system_wrapper_tb.v (2761, 2013-05-29)
Xilinx_AXI\tb\verilog\lite_system_wrapper_tb.v (2763, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\verilog (0, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_master_1.0\xgui (0, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\verilog (0, 2013-05-29)
Xilinx_AXI\ip_repo_complete\YourCompanyName.com_user_axi_lite_slave_1.0\xgui (0, 2013-05-29)
... ...

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2013 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 1.0 Date Last Modified: 29052013 Date Created: 29052013 Associated Filename: xapp1168.zip Associated Document: XAPP1168, Packaging Custom AXI IP for Vivado IP Integrator Supported Device(s): Virtex-7 FPGAs, Kintex-7 FPGAs, Artix-7 FPGAs ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 29MAY2013 1.0 Initial Xilinx release. ========================================================================= 2. OVERVIEW This readme describes how to use the files that come with XAPP1168 The files contained in this zip file are example AXI IP to be packaged for Vivado IP integrator. 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * Xilinx Vivado 2013.1 or higher 4. DESIGN FILE HIERARCHY The directory structure underneath this top-level folder is described below: |-- hdl | `-- verilog | |-- axi_lite_master.v | |-- axi_lite_slave.v | |-- axi_master.v | |-- axi_slave.v | |-- axi_stream_master.v | `-- axi_stream_slave.v |-- readme.txt |-- source.tcl `-- tb `-- verilog |-- axi_stream_system_wrapper_tb.v |-- axi_system_wrapper_tb.v `-- lite_system_wrapper_tb.v 5. INSTALLATION AND OPERATING INSTRUCTIONS 1) Install the Xilinx Vivado 2013.1 or later tools. 2) From this directory: vivado -source source.tcl 6. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database or to create a WebCase.

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