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assets (0, 2020-04-24)
assets\screenshot1.png (1338608, 2020-04-24)
assets\screenshot2.png (373419, 2020-04-24)
blockly-edit.html (8296, 2020-04-24)
blocks (0, 2020-04-24)
blocks\assignment.js (2835, 2020-04-24)
blocks\behavior.js (2144, 2020-04-24)
blocks\core (0, 2020-04-24)
blocks\core\blockly_compressed.js (609791, 2020-04-24)
blocks\core\blocks_compressed.js (75622, 2020-04-24)
blocks\functions.js (6663, 2020-04-24)
blocks\initial (0, 2020-04-24)
blocks\initial\init.js (2289, 2020-04-24)
blocks\logic.js (987, 2020-04-24)
blocks\loops.js (1705, 2020-04-24)
blocks\math.js (1812, 2020-04-24)
blocks\module.js (959, 2020-04-24)
blocks\numbers.js (2583, 2020-04-24)
blocks\operators.js (1626, 2020-04-24)
blocks\rewrite (0, 2020-04-24)
blocks\rewrite\createVariablesButtonHandler.js (3308, 2020-04-24)
blocks\rewrite\customExtensions.js (5652, 2020-04-24)
blocks\task (0, 2020-04-24)
blocks\task\core.js (3208, 2020-04-24)
blocks\task\task.js (8593, 2020-04-24)
blocks\timing.js (2358, 2020-04-24)
blocks\values.js (1993, 2020-04-24)
blocks\variables_dynamic (0, 2020-04-24)
blocks\variables_dynamic\core.js (8343, 2020-04-24)
blocks\variables_dynamic\variables.js (6126, 2020-04-24)
generator (0, 2020-04-24)
generator\verilog.js (9502, 2020-04-24)
generator\verilog (0, 2020-04-24)
generator\verilog\assignment.js (2023, 2020-04-24)
generator\verilog\behavior.js (1190, 2020-04-24)
generator\verilog\functions.js (4405, 2020-04-24)
generator\verilog\initBlocks.js (2746, 2020-04-24)
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# blocklyTB # blocklyTB is a visual programming tool for writing Verilog testbench. It is based on the secondary development of Google Blockly and assists learning FPGA for educational purposes.   ## [Visit online](https://github.com/yasminyt/blocklyTB/blob/master/https://yasminyt.github.io/blocklyTB/) You can access and use it [online](https://github.com/yasminyt/blocklyTB/blob/master/https://yasminyt.github.io/blocklyTB/), but first make sure that you already have the FPGA design file (file ending in .v) or the xml design file exported by blocklyTB. You can also save the [link](https://github.com/yasminyt/blocklyTB/blob/master/https://yasminyt.github.io/blocklyTB/) as a favorite for future visits. Of course, you can also get the [source code](https://github.com/yasminyt/blocklyTB/blob/master/https://github.com/yasminyt/blocklyTB) locally, visit blocklyTB/index.html in your browser to use. ## Features ## Theses are the main features of blocklyTB: - Supports most Verilog syntaxes, enabling basic testbench design. - Supports automatic DUT instantiation. Just upload the completed FPGA design (only Verilog language is supported), blocklyTB will automatically complete the instantiation process required by the testbench. - Supports to save the design of blocklyTB locally. you can import it again to continue the design next time. - Can create different types of variables, such as reg, wire, parameter, localparamter, integer, etc. - Implemented encapsulation and reuse of the task. - blocklyTB adds several system functions commonly used in Verilog, such as $ time, $ monitor, $ random, etc., and common file I/O functions. - Generate corresponding Verilog code in real time and display it in format, which can be copied or downloaded. - Some other features provided by [Google Blockly](https://github.com/yasminyt/blocklyTB/blob/master/https://developers.google.com/blockly/).

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