关于各种基本单元的verilog模块实验
所属分类：VHDL/FPGA/Verilog
开发工具：C/C++
文件大小：100KB
下载次数：0
上传日期：2020-04-30 10:18:56
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说明： 关于各种基本单元的verilog模块实验，适合感兴趣的学习者学习，可以提高自己的能力，大家可以多交流哈
(Verilog module experiments on various basic units are suitable for interested learners to learn and improve their abilities. You can communicate more)
文件列表:
verilog_code_673\add_beh.v (2579, 1998-10-18)
verilog_code_673\add_rtl.v (4667, 1998-10-18)
verilog_code_673\add_sim.v (6707, 1998-10-18)
verilog_code_673\afifo_beh.v (4130, 1998-10-26)
verilog_code_673\afifo_rtl.v (5129, 1998-10-26)
verilog_code_673\afifo_sim.v (6360, 1998-10-26)
verilog_code_673\checksum.v (1806, 1998-10-18)
verilog_code_673\check_sim.v (5607, 1999-04-14)
verilog_code_673\cnt_beh.v (2401, 1999-01-01)
verilog_code_673\cnt_rtl.v (2728, 1999-04-14)
verilog_code_673\cnt_sim.v (7230, 1998-10-18)
verilog_code_673\crc_beh.v (3188, 1998-10-18)
verilog_code_673\crc_rtl.v (2860, 1998-10-18)
verilog_code_673\crc_sim.v (4257, 1998-10-18)
verilog_code_673\dramcon_beh.v (5025, 1998-11-11)
verilog_code_673\dramcon_rtl.v (4993, 1998-10-27)
verilog_code_673\dramcon_sim.v (9691, 1999-01-01)
verilog_code_673\dual.v (1755, 1998-10-18)
verilog_code_673\dual_sim.v (3279, 1998-10-18)
verilog_code_673\encr_beh.v (3311, 1998-10-18)
verilog_code_673\encr_rtl.v (2930, 1998-10-18)
verilog_code_673\encr_sim.v (3484, 1998-10-18)
verilog_code_673\fpdramcon_beh.v (5607, 2004-10-14)
verilog_code_673\fpdramcon_rtl.v (5588, 1998-11-11)
verilog_code_673\fullcase.v (1149, 1998-10-18)
verilog_code_673\fullcase1.v (1183, 1998-10-18)
verilog_code_673\fullcase2.v (1153, 1998-10-18)
verilog_code_673\hamdec.v (2846, 1998-10-19)
verilog_code_673\hamgen.v (1373, 1998-10-19)
verilog_code_673\ham_sim.v (3692, 1998-10-18)
verilog_code_673\jk_beh.v (1522, 1998-10-18)
verilog_code_673\jk_rtl.v (1586, 1998-10-18)
verilog_code_673\jk_sim.v (3953, 1998-10-18)
verilog_code_673\lfsr2_beh.v (3185, 1998-10-18)
verilog_code_673\lfsr2_rtl.v (3105, 1998-10-18)
verilog_code_673\lfsr_beh.v (2943, 1998-10-18)
verilog_code_673\lfsr_rtl.v (2856, 1998-10-18)
verilog_code_673\lfsr_sim.v (2846, 1998-10-18)
verilog_code_673\mealy_beh.v (2920, 1998-10-18)
verilog_code_673\mealy_rtl.v (3196, 1998-10-18)
... ...
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