caiyang
所属分类：其他
开发工具：Verilog
文件大小：1854KB
下载次数：0
上传日期：2020-05-01 17:46:03
上 传 者：
唧唧爱baby
说明： 使用MAX10内置12位采样芯片，对外部电压量进行采样，采样率为1mhz
(Using max10 built-in 12 bit sampling chip to sample the external voltage, the sampling rate is 1 MHz)
文件列表:
caiyang\.qsys_edit\caiyang2_5.xml (82907, 2018-12-08)
caiyang\.qsys_edit\caiyang2_5_schematic.nlv (1482, 2018-12-08)
caiyang\.qsys_edit\caiyang3_0.xml (82907, 2018-12-07)
caiyang\.qsys_edit\caiyang3_0_schematic.nlv (1482, 2018-12-07)
caiyang\.qsys_edit\caiyang6.xml (82907, 2018-12-10)
caiyang\.qsys_edit\caiyang6_1.xml (82907, 2018-12-10)
caiyang\.qsys_edit\caiyang6_1_schematic.nlv (1482, 2018-12-10)
caiyang\.qsys_edit\caiyang6_schematic.nlv (1482, 2018-12-10)
caiyang\.qsys_edit\caiyangaa.xml (82907, 2018-12-10)
caiyang\.qsys_edit\caiyangaa_schematic.nlv (1482, 2018-12-10)
caiyang\.qsys_edit\caiyangcc.xml (82907, 2018-12-07)
caiyang\.qsys_edit\caiyangcc_schematic.nlv (1482, 2018-12-07)
caiyang\.qsys_edit\ciayng6.xml (82907, 2018-12-10)
caiyang\.qsys_edit\ciayng6_schematic.nlv (1482, 2018-12-10)
caiyang\.qsys_edit\filters.xml (66, 2018-12-07)
caiyang\.qsys_edit\kkk.xml (82907, 2019-10-09)
caiyang\.qsys_edit\kkk_schematic.nlv (1482, 2019-10-09)
caiyang\.qsys_edit\preferences.xml (385, 2019-10-09)
caiyang\caiyang2_5\caiyang2_5.bsf (7166, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5.cmp (1374, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5.html (146836, 2020-03-29)
caiyang\caiyang2_5\caiyang2_5.ppf (1200, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5.xml (37263, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5_bb.v (700, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5_generation.rpt (1505, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5_inst.v (1328, 2018-12-08)
caiyang\caiyang2_5\caiyang2_5_inst.vhd (2712, 2018-12-08)
caiyang\caiyang2_5\synthesis\caiyang2_5.debuginfo (64253, 2018-12-08)
caiyang\caiyang2_5\synthesis\caiyang2_5.qip (41091, 2018-12-08)
caiyang\caiyang2_5\synthesis\caiyang2_5.v (2264, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\altera_modular_adc_control.sdc (7905, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\altera_modular_adc_control.v (6753, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\altera_modular_adc_control_avrg_fifo.v (7713, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\altera_modular_adc_control_fsm.v (34944, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\caiyang2_5_modular_adc_0.v (3692, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\chsel_code_converter_sw_to_hw.v (13365, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\fiftyfivenm_adcblock_primitive_wrapper.v (13509, 2018-12-08)
caiyang\caiyang2_5\synthesis\submodules\fiftyfivenm_adcblock_top_wrapper.v (14400, 2018-12-08)
caiyang\caiyang2_5.qsys (12959, 2018-12-08)
caiyang\caiyang2_5.sopcinfo (63973, 2018-12-08)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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