test1
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：6559KB
下载次数：0
上传日期：2020-05-17 11:06:39
上 传 者：
枕惊鸿
说明： 试用Verilog HDL语言，设计一个七段数码管译码器，用该电路显示0~9共10个字符，要求首先使用Modelsim软件进行功能仿真，然后使用Quartus软件综合，并下载到开发板进行电路功能测试。
(Using Verilog HDL language, a seven segment digital tube decoder is designed. The circuit displays 10 characters from 0 to 9. It is required to first use Modelsim software for function simulation, then use quartus software for synthesis, and download it to the development board for circuit function test.)
文件列表:
test1\c5_pin_model_dump.txt (4875, 2020-05-15)
test1\db (0, 2020-05-15)
test1\db\.cmp.kpt (202, 2020-05-15)
test1\db\logic_util_heursitic.dat (1320, 2020-05-15)
test1\db\prev_cmp_t1.qmsg (45711, 2020-05-15)
test1\db\seg7.(0).cnf.cdb (1402, 2020-02-25)
test1\db\seg7.(0).cnf.hdb (792, 2020-02-25)
test1\db\seg7.asm.qmsg (2255, 2020-05-15)
test1\db\seg7.asm.rdb (1398, 2020-05-15)
test1\db\seg7.cbx.xml (86, 2020-05-15)
test1\db\seg7.cmp.bpm (698, 2020-05-15)
test1\db\seg7.cmp.cdb (22978, 2020-05-15)
test1\db\seg7.cmp.hdb (117199, 2020-05-15)
test1\db\seg7.cmp.idb (961, 2020-05-15)
test1\db\seg7.cmp.logdb (10574, 2020-05-15)
test1\db\seg7.cmp.rdb (27997, 2020-05-15)
test1\db\seg7.cmp_merge.kpt (207, 2020-05-15)
test1\db\seg7.cyclonev_io_sim_cache.ff_0c_fast.hsd (1052458, 2020-05-15)
test1\db\seg7.cyclonev_io_sim_cache.ff_85c_fast.hsd (1054544, 2020-05-15)
test1\db\seg7.cyclonev_io_sim_cache.tt_0c_slow.hsd (1054327, 2020-05-15)
test1\db\seg7.cyclonev_io_sim_cache.tt_85c_slow.hsd (1067414, 2020-05-15)
test1\db\seg7.db_info (140, 2020-05-15)
test1\db\seg7.fit.qmsg (54499, 2020-05-15)
test1\db\seg7.hier_info (412, 2020-05-15)
test1\db\seg7.hif (420, 2020-05-15)
test1\db\seg7.ipinfo (163, 2020-05-15)
test1\db\seg7.lpc.html (372, 2020-05-15)
test1\db\seg7.lpc.rdb (403, 2020-05-15)
test1\db\seg7.lpc.txt (1060, 2020-05-15)
test1\db\seg7.map.ammdb (129, 2020-05-15)
test1\db\seg7.map.bpm (657, 2020-05-15)
test1\db\seg7.map.cdb (2604, 2020-05-15)
test1\db\seg7.map.hdb (11585, 2020-05-15)
test1\db\seg7.map.kpt (205, 2020-05-15)
test1\db\seg7.map.qmsg (4544, 2020-05-15)
test1\db\seg7.map.rdb (1354, 2020-05-15)
test1\db\seg7.map_bb.cdb (1885, 2020-05-15)
test1\db\seg7.map_bb.hdb (10548, 2020-05-15)
test1\db\seg7.pplq.rdb (296, 2020-05-15)
test1\db\seg7.pre_map.hdb (11732, 2020-05-15)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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