说明：  之前上载了一个串口接收模块，确实漏了一个文件，这次重新发一下。修改了PARITY_CHECK模块，这样可以支持无校验的应用。这个串口接收模块可以使用parameter参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。
(I had uploaded a serial port receiving module, but a file was indeed missed. This time, I will send it again. Modified PARITY_ Check module, which can support the application without parity. The serial port receiving module can use parameter to configure the transmission rate, transmission bit width and verification. Using Verilog voice programming. Users can configure parameters according to the requirements of serial port, and configure FIFO according to the size of buffer. The frame error (stop bit is not high), check error and read FIFO timeout (when FIFO is full, there is new data to) are checked.)