Xilinx_Ethernet_1G
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：18219KB
下载次数：0
上传日期：2020-05-24 08:35:22
上 传 者：
sh-1993
说明： FPGA 1Gbps以太网与UDP数据传输芯片评估
(FPGA 1Gbps ETHERNET With UDP Data Transfer for Chip Evaluation)
文件列表:
.cxl.ip (0, 2020-05-24)
.cxl.ip\incl (0, 2020-05-24)
.cxl.ip\incl\HBM_nc.vp (2369575, 2020-05-24)
.cxl.ip\incl\HBM_questa.vp (357012, 2020-05-24)
.cxl.ip\incl\HBM_vcs.vp (2368065, 2020-05-24)
.cxl.ip\incl\adv_vphy_defs.v (43521, 2020-05-24)
.cxl.ip\incl\av_pat_gen_v1_0_0_defs.v (2449, 2020-05-24)
.cxl.ip\incl\axi4mm_axi_bridge.vh (5910, 2020-05-24)
.cxl.ip\incl\axi_infrastructure_header.vh (8325, 2020-05-24)
.cxl.ip\incl\axi_infrastructure_v1_1_0.vh (8325, 2020-05-24)
.cxl.ip\incl\axi_traffic_gen_v2_0_18_defines.v (10561, 2020-05-24)
.cxl.ip\incl\axi_traffic_gen_v3_0_3_defines.v (10560, 2020-05-24)
.cxl.ip\incl\axi_vdma_v6_3_5.vh (12217, 2020-05-24)
.cxl.ip\incl\axidma_fifo.vh (37804, 2020-05-24)
.cxl.ip\incl\axis_infrastructure_v1_1_0.vh (12211, 2020-05-24)
.cxl.ip\incl\axis_interconnect_v1_1_15.vh (12175, 2020-05-24)
.cxl.ip\incl\bs_switch_v1_0_0_bs.vh (35519, 2020-05-24)
.cxl.ip\incl\bs_switch_v1_0_0_bs_ext.vh (36464, 2020-05-24)
.cxl.ip\incl\bs_switch_v1_0_0_in.vh (1552, 2020-05-24)
.cxl.ip\incl\canfd_v1_0_10_can_ip_pkg.vh (4324, 2020-05-24)
.cxl.ip\incl\cpri_v8_9_1_hard_fec.vh (5620, 2020-05-24)
.cxl.ip\incl\defines.vh (53, 2020-05-24)
.cxl.ip\incl\displayport_v7_0_9_rx_defs.v (47298, 2020-05-24)
.cxl.ip\incl\displayport_v7_0_9_rx_dpcd_defs.v (20129, 2020-05-24)
.cxl.ip\incl\displayport_v7_0_9_tx_defs.v (32708, 2020-05-24)
.cxl.ip\incl\displayport_v8_0_1_rx_defs.v (49413, 2020-05-24)
.cxl.ip\incl\displayport_v8_0_1_rx_dpcd_defs.v (20129, 2020-05-24)
.cxl.ip\incl\displayport_v8_0_1_tx_defs.v (32773, 2020-05-24)
.cxl.ip\incl\dma_defines.svh (12331, 2020-05-24)
.cxl.ip\incl\dma_defines.vh (701, 2020-05-24)
.cxl.ip\incl\dma_pcie_axis_cc_if.svh (816, 2020-05-24)
.cxl.ip\incl\dma_pcie_axis_cq_if.svh (849, 2020-05-24)
.cxl.ip\incl\dma_pcie_axis_rc_if.svh (852, 2020-05-24)
.cxl.ip\incl\dma_pcie_axis_rq_if.svh (813, 2020-05-24)
.cxl.ip\incl\dma_pcie_c2h_crdt_if.svh (1321, 2020-05-24)
.cxl.ip\incl\dma_pcie_dsc_in_if.svh (306, 2020-05-24)
.cxl.ip\incl\dma_pcie_dsc_out_if.svh (435, 2020-05-24)
.cxl.ip\incl\dma_pcie_fabric_input_if.svh (697, 2020-05-24)
.cxl.ip\incl\dma_pcie_fabric_output_if.svh (1680, 2020-05-24)
... ...
# Xilinx_Ethernet_1G
FPGA 1Gbps ETHERNET With UDP Data Transfer for Chip Evaluation
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