利用ISE的SDRAM设计的FIFO实验
所属分类:VHDL/FPGA/Verilog
开发工具:C/C++
文件大小:4KB
下载次数:0
上传日期:2020-06-11 09:47:33
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ningqingxue
说明: 利用ISE的SDRAM设计的FIFO实验,适合感兴趣的学习者学习,可以提高自己的能力,大家可以多交流哈
(FIFO experiment designed by ISE's SDRAM is suitable for interested learners to learn, and can improve their ability, so that everyone can communicate more)
文件列表:
fifo\interface.v (4499, 2012-03-04)
fifo\sram.v (4378, 2012-02-23)
fifo\t_fifo.v (2455, 2012-03-04)
fifo (0, 2020-04-03)
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