数字时钟
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：2381KB
下载次数：0
上传日期：2020-06-16 22:07:40
上 传 者：
雪后初晴
说明： 实现计时，置数，闹钟设置，切换显示等
1.硬件资源：FPGA开发板一块，电源线一根，下载器一个
2.开发板用到的资源：三颗独立按键，一位拨码开关，八位七段数码显示器，
蜂鸣器
3.功能设计：时钟功能，校时功能，闹钟功能
整个系统分为7大模块
(Realize timing, setting, alarm setting, switching display, etc
1. Hardware resources: one FPGA development board, one power cord and one Downloader
2. Resources used in the development board: three independent buttons, one dial switch, eight seven segment digital display,
Buzzer
3. Function design: clock function, timing function, alarm function
The whole system is divided into seven modules)
文件列表:
数字时钟\FPGA\beep.v (415, 2019-11-08)
数字时钟\FPGA\beep.v.bak (383, 2019-11-07)
数字时钟\FPGA\clock.asm.rpt (7716, 2019-11-07)
数字时钟\FPGA\clock.cdf (336, 2019-11-07)
数字时钟\FPGA\clock.done (26, 2019-11-08)
数字时钟\FPGA\clock.fit.rpt (166488, 2019-11-07)
数字时钟\FPGA\clock.fit.smsg (513, 2019-11-07)
数字时钟\FPGA\clock.fit.summary (606, 2019-11-07)
数字时钟\FPGA\clock.flow.rpt (6601, 2019-11-08)
数字时钟\FPGA\clock.map.rpt (33139, 2019-11-08)
数字时钟\FPGA\clock.map.smsg (390, 2019-11-08)
数字时钟\FPGA\clock.map.summary (671, 2019-11-08)
数字时钟\FPGA\clock.pin (27110, 2019-11-07)
数字时钟\FPGA\clock.pof (524497, 2019-11-07)
数字时钟\FPGA\clock.qpf (1291, 2019-11-05)
数字时钟\FPGA\clock.qsf (4476, 2019-11-08)
数字时钟\FPGA\clock.sof (240798, 2019-11-07)
数字时钟\FPGA\clock.sta.rpt (114696, 2019-11-07)
数字时钟\FPGA\clock.sta.summary (649, 2019-11-07)
数字时钟\FPGA\clock_top.v (3257, 2019-11-07)
数字时钟\FPGA\clock_top.v.bak (583, 2019-11-05)
数字时钟\FPGA\db\clock.(0).cnf.cdb (3608, 2019-11-08)
数字时钟\FPGA\db\clock.(0).cnf.hdb (1918, 2019-11-08)
数字时钟\FPGA\db\clock.(1).cnf.cdb (3306, 2019-11-08)
数字时钟\FPGA\db\clock.(1).cnf.hdb (1187, 2019-11-08)
数字时钟\FPGA\db\clock.(2).cnf.cdb (23920, 2019-11-08)
数字时钟\FPGA\db\clock.(2).cnf.hdb (2970, 2019-11-08)
数字时钟\FPGA\db\clock.(3).cnf.cdb (3486, 2019-11-08)
数字时钟\FPGA\db\clock.(3).cnf.hdb (1084, 2019-11-08)
数字时钟\FPGA\db\clock.(4).cnf.cdb (9257, 2019-11-08)
数字时钟\FPGA\db\clock.(4).cnf.hdb (3688, 2019-11-08)
数字时钟\FPGA\db\clock.(5).cnf.cdb (4803, 2019-11-08)
数字时钟\FPGA\db\clock.(5).cnf.hdb (1986, 2019-11-08)
数字时钟\FPGA\db\clock.(6).cnf.cdb (2058, 2019-11-08)
数字时钟\FPGA\db\clock.(6).cnf.hdb (897, 2019-11-08)
数字时钟\FPGA\db\clock.(7).cnf.cdb (1838, 2019-11-08)
数字时钟\FPGA\db\clock.(7).cnf.hdb (1392, 2019-11-08)
数字时钟\FPGA\db\clock.ae.hdb (18988, 2019-11-08)
数字时钟\FPGA\db\clock.amm.cdb (623, 2019-11-07)
数字时钟\FPGA\db\clock.asm.qmsg (2248, 2019-11-07)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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