filter
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8KB
下载次数：17
上传日期：2011-07-08 10:47:49
上 传 者：
baomeng
说明： 分享数字滤波器的FPGA实现，基于Verilog语言的硬件描述，如果你想在FPGA上实现，会很有用的哦...
(Share digital filter FPGA implementation based on Verilog hardware description language, if you want to achieve in the FPGA, will be very useful oh ...)
文件列表:
c6 (0, 2011-07-08)
c6\6-18 (0, 2011-07-08)
c6\6-18\iir_pipeline.v (1295, 2007-09-17)
c6\6-20 (0, 2011-07-08)
c6\6-20\iir_par.v (2401, 2007-09-17)
c6\6-23 (0, 2011-07-08)
c6\6-23\rrc_128.coe (709, 2007-10-06)
c6\6-4 (0, 2011-07-08)
c6\6-4\FIR_lowpass.v (1525, 2007-10-09)
c6\6-5 (0, 2011-07-08)
c6\6-5\mult.xco (1243, 2007-09-12)
c6\6-5\ser_fir.v (4201, 2007-09-12)
c6\6-6 (0, 2011-07-08)
c6\6-6\fir.v (2661, 2007-09-12)
c6\6-6\mult.xco (1243, 2007-09-12)
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