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project-41 (0, 2020-06-30)

project-1 E Quotes: Great relationships aren't built in a day - great relationships are built daily. Train your mind to be stronger than your emotion or else you will loose yourself every time. Be valuable not available. Kindness is a beauty that never fades. Do good, it will come back to you in unexpected ways. A person who chases two rabbits catches neither. stay focused on a goal. The Cortex-M3 and Cortex-M4 Processors: The Cortex-M3 and Cortex-M4 are processors designed by ARM. The Cortex-M3 processor was the first of the Cortex generation of processors, released by ARM in 2005. The Cortex-M4 processor was released in 2010. The Cortex-M3 and Cortex-M4 processors use a 32-bit architecture. Internal registers in the register bank, the data path, and the bus interfaces are all 32 bits wide. The Instruction Set Architecture (ISA) in the Cortex-M processors is called the Thumb ISA and is based on Thumb-2 Technology which supports a mixture of 16-bit and 32-bit instructions. The Cortex-M3 and Cortex-M4 processors have: Three-stage pipeline design Harvard bus architecture with unified memory space: instructions and data use the same address space 32-bit addressing, supporting 4GB of memory space On-chip bus interfaces based on ARM AMBA (Advanced Microcontroller Bus Architecture) Technology, which allow pipelined bus operations for higher throughput An interrupt controller called NVIC (Nested Vectored Interrupt Controller) supporting up to 240 interrupt requests and from 8 to 256 interrupt priority levels (dependent on the actual device implementation) Support for various features for Operating System(OS) implementation such as a system tick timer, shadowed stack pointer Sleep mode support and various low power features Support for an optional Memory Protection Unit(MPU) to provide memory protection features like programmable memory, or access permission control Support for bit-data accesses in two specific memory regions using a feature called Bit Band The option of being used in single processor or multi-processor designs The ISA used in Cortex-M3 and Cortex-M4 processors provides a wide range of instructions: General data processing, including hardware divide instructions Memory access instructions supporting 8-bit, 16-bit, 32-bit, and ***-bit data, as well as instructions for transferring multiple 32-bit data Instructions for bit field processing Multiply Accumulate (MAC) and saturate instructions Instructions for branches, conditional branches and function calls Instructions for system control, OS support, etc. Both the Cortex-M3 and Cortex-M4 processors are widely used in modern microcontroller products, as well as other specialized silicon designs such as System on Chips (SoC) and Application Specific Standard Products (ASSP). In general, the ARM Cortex-M processors are regarded as RISC (Reduced Instruction Set Computing) processors. Some might argue that certain characteristics of the Cortex-M3 and Cortex-M4 processors, such as the rich instruction set and mixed instruction sizes, are closer to CISC (Complex Instruction Set Computing) processors. But as processor technologies advance, the instruction sets of most RISC processors are also getting more complex, so much so that this traditional boundary between RISC and CISC processor definition can no longer be applied. The Cortex-M Processor Family: The Cortex-M3 and Cortex-M4 processors are two of the products in the ARM Cortex-M processor family. The whole Cortex-M processor family is shown in figure below. Figure: The Cortex-M processor family The Cortex-M3 and Cortex-M4 processors are based on ARMv7-M architecture. Both are high-performance processors that are designed for microcontrollers. Because the Cortex-M4 processor has Single Instruction Multiple Data (SIMD), fast Multiply Accumulate (MAC), and saturate arithmetic instructions, it can also carry out some of the digital signal processing applications that traditionally have been carried out by a separate Digital Signal Processor (DSP). The Cortex-M0, Cortex-M0+, and the Cortex-M1 processors are based on ARMv6-M, which has a smaller instruction set. Both Cortex-M0 and Cortex-M0+ are very small size in terms of gate count, with just about 12K gates in minimum configuration, and are ideal for low-cost microcontroller products. The Cortex-M0+ processor has the most state-of-the-art low power optimizations, and has more available optional features. The Cortex-M1 processor is designed specifically for FPGA applications. It has Tightly Coupled Memory (TCM) features that can be implemented using memories inside the FPGA, and the design allows high clock frequency operations in advanced FPGA. For general data processing and I/O control tasks, the Cortex-M0 and Cortex-M0+ processors have excellent energy efficiency due to the low gate count design. But for applications with complex data processing requirements, they may take more instructions and clock cycles. In above case, the Cortex-M3 or Cortex-M4 processor would be more suitable, because the additional instructions available in these processors allow the processing to be carried out with fewer instructions compared to ARMv6-M architecture. As a result, we need different processors for different applications. Advantages of the Cortex-M Processors: 1. Low Power: Compared to other 32-bit processor designs, Cortex -M processors are relatively small. The Cortex-M processor designs are also optimized for low power consumption. Currently, many Cortex-M microcontrollers have power consumption of less than 200 mA/MHz, with some of them well under 100 mA/MHz. the Cortex-M processors also include support for sleep mode features and can be used with various advanced ultra-low power design technologies. 2. Code Density: The Thumb ISA provides excellent code density results in reduce cost and power consumption by using a microcontroller with smaller flash memory size, and chip manufacturers can produce microcontroller chips with smaller packages. 3. Interrupts: The Cortex-M3 and Cortex-M4 processors have a configurable interrupt controller design, which can support up to 240 vectored interrupts and multiple levels of interrupt priorities (from 8 to 256 levels). Nesting of interrupts is automatically handled by hardware, and the interrupt latency is only 12 clock cycles for systems with zero wait state memory. The interrupt processing capability makes the Cortex-M processors suitable for many real-time control applications. 4. Ease of use, C friendly: The Cortex-M processors are very easy to use. In fact, they are easier than compared to many 8-bit processors because Cortex-M processors have a simple, linear memory map, and there are no special architectural restrictions, which you often find in 8-bit microcontrollers (e.g., memory banking, limited stack levels, etc.). You can program almost everything in C including the interrupt handlers. 5. Scalability: The Cortex -M processor family allows easy scaling of designs from low-cost, simple microcontrollers costing less than a dollar to high-end microcontrollers running at 200MHz or more. 6. Debug Features: With standard design features, which you can find in most microcontrollers like halting and single stepping, you can also generate a trace to capture program flow, data changes, profiling information, and so on. 7. OS Support: The Cortex-M processors are designed with OS applications in mind. A number of features are available to make OS implementation easier and make OS operations more efficient. Currently there are over 30 embedded OSs available for Cortex-M processors. 8. Versatile System Features: The Cortex-M3 and Cortex-M4 processors support a number of system features such as bit addressable memory range (bit band feature) and Memory Protection Unit(MPU). 9. Software Portability and Reusability: Since the architecture is very C friendly, you can program almost everything in standard ANSI C. One of ARM’s initiatives called CMSIS (Cortex Microcontroller Software Interface Standard) makes programming for Cortex-M processor based products even easier by providing standard header files and an API for standard Cortex-M processor functions. This allows better software reusability and also makes porting application code easier. 10. Choices (devices, tools, OS, etc.): A wide range of choices for software development/debug tools, embedded OS, middleware, etc. Introduction to the Architecture: The Cortex-M3 and Cortex-M4 Processors are based on the ARMv7-M architecture. The original ARMv7-M architecture was defined when the Cortex-M3 processor was developed, and when the Cortex-M4 was released, the architecture was extended to included additional instructions and architectural features. The extended architecture is sometimes called ARMv7E-M architecture. Programmer’s Model: Operation Modes and States: The Cortex-M3 and Cortex-M4 processors have two operation states and two modes. In addition, the processors can have privileged and unprivileged access levels. These are shown in Figure 1. Figure 1: Operation states and modes Access Level: 1. privileged Access Level: Can access all resources in the processor 2. Unprivileged Access Level: Some memory regions are inaccessible, and a few operations cannot be used. In some documents, the unprivileged access level might also be referred as “User” state, a term inherited from ARM7TDMI. Software can switch the processor in privileged Thread mode to unprivileged Thread mode. However, it cannot switch itself back from unprivileged to privileged. If this is needed, the processor must use the exception mechanism to handle the switch. The separation of privileged and unprivileged access levels allows system designers to develop robust embedded systems by providing a mechanism to safeguard memory accesses to critical regions and by providing a basic security model. E.x: A system can contain an embedded OS kernel that executes in privileged access level, and application tasks which execute in unprivileged access level. In this way, we can set up memory access permissions using the Memory Protection Unit (MPU) to prevent an application task from corrupting memory and peripherals used by the OS kernel and other tasks. If an application task crashes, the remaining application tasks and the OS kernel can still continue to run. Besides the differences in memory access permission and access to several special instructions, the programmer’s model of the privileged access level and unprivileged access level are almost the same. Note that almost all of the NVIC registers are privileged access only. Operation States: 1. Debug State: When the processor is halted (e.g., by the debugger, or after hitting a breakpoint), it enters debug state and stops executing instructions. 2. Thumb State: If the processor is running program code (Thumb instructions), it is in the Thumb state. Unlike classic ARM processors like ARM7TDMI, there is no ARM state because the Cortex-M processors do not support the ARM instruction set. Operation Modes: 1. Handler Mode: Processor enters when executing an exception handler such as an Interrupt Service Routine (ISR). When in handler mode, the processor always has privileged access level. 2. Thread Mode: Processor enters when executing normal application code. The processor can be either in privileged access level or unprivileged access level. This is controlled by a special register called “CONTROL.” Thread mode and Handler mode have very similar programmer’s models. However, Thread mode can switch to using a separate shadowed Stack Pointer (SP). This allows the stack memory for application tasks to be separated from the stack used by the OS kernel, thus allowing better system reliability. By default, the Cortex-M processors start in privileged Thread mode and in Thumb state. In many simple applications, there is no need to use the unprivileged Thread model and the shadowed SP at all as shown in figure 2 below. Unprivileged Thread model is not available in the Cortex-M0 processor, but is optional in the Cortex-M0+ processor. Figure 2: In simple applications, the unprivileged Thread mode can be unused The debug state is used for debugging operations only. This state is entered by a halt request from the debugger, or by debug events generated from debug components in the processor. This state allows the debugger to access or change the processor register values. The system memory, including peripherals inside and outside the processor, can be accessed by the debugger in either Thumb state or debug state. Registers: The Cortex-M3 and Cortex-M4 processors have a number of registers inside the processor core to perform data processing and control. Most of these registers are grouped in a unit called the register bank. Each data processing instruction specifies the operation required, the source register(s), and the destination register(s) if applicable. In the ARM architecture, if data in memory is to be processed, it has to be loaded from the memory to registers in the register bank, processed inside the processor, and then written back to the memory, if needed. This is commonly called a “load-store architecture.” By having a sufficient number of registers in the register bank, this arrangement is easy to use, and allows efficient program code to be generated using C compilers. The register bank in the Cortex-M3 and Cortex-M4 processors has 16 registers. Thirteen of them are general purpose 32-bit registers, and the other three have special uses, as can be seen in Figure 3. Figure 3: Registers in the Register Bank R0 to R12: Registers R0 to R12 are general purpose registers. The first eight (R0 to R7) are also called low registers. Due to the limited available space in the instruction set, many 16-bit instructions can only access the low registers. The high registers (R8 to R12) can be used with 32-bit instructions, and a few with 16-bit instructions, like MOV(move). The initial values of R0 to R12 are undefined. R13 - Stack Pointer (SP): R13 is called/referred as Stack Pointer. It is used for accessing the stack memory via PUSH and POP operations. Physically there are two different Stack Pointers: Main Stack Pointer (MSP, or SP_main in some ARM documentation) is the default Stack Pointer. It is selected after reset, or when the processor is in Handler Mode. Process Stack Pointer (PSP, or SP_process in some ARM documentation). The PSP can only be used in Thread Mode. The selection of Stack Pointer is determined by a special register called CONTROL. In normal programs, only one of these Stack Pointers will be visible. Both MSP and PSP are 32-bit, but the lowest two bits of the Stack Pointers (either MSP or PSP) are always zero, and writes to these two bits are ignored. In ARM Cortex-M processors, PUSH and POP are always 32-bit, and the addresses of the transfers in stack operations must be aligned to 32-bit word boundaries. For most cases, it is not necessary to use the PSP if the application doesn’t require an embedded OS. Many simple applications can rely on the MSP completely. The PSP is normally used when an embedded OS is involved, where the stack for the OS kernel and application tasks are separated. The initial value of PSP is undefined, and the initial value of MSP is taken from the first word of the memory during the reset sequence. R14 - Link Register (LR): R14 is also called the Link Register (LR). This is used for holding the return address when calling a function or subroutine. At the end of the function or subroutine, the program control can return to the calling program and resume by loading the value of LR into the Program Counter (PC). When a function or subroutine call is made, the value of LR is updated automatically. If a function needs to call another function or subroutine, it needs to save the value of LR in the stack first. Otherwise, the current value in LR will be lost when the function call is made. During exception handling, the LR is also updated automatically to a special EXC_RETURN (Exception Return) value, which is then used for triggering the exception return at the end of the exception handler. Although the return address values in the Cortex-M processors are always even (bit 0 is zero because the instructions must be aligned to half-word addresses), bit 0 of LR is readable and writeable. Some of the branch/call operations require that bit zero of LR (or any register being used) be set to 1 to indicate Thumb state. R15 - Program Counter (PC): R15 is the Program Counter (PC). It is readable and writeable: A read returns the current instruction address plus 4 (this is due to the pipeline nature of the design, and compatibility requirement with the ARM7TDMI processor). Writing to PC (e.g., using data transfer/processing instructions) causes a branch operation. Since the instructions must be aligned to half-word or word addresses, the Least Significant Bit (LSB) of the PC is zero. However, when using some of the branch/memory read instructions to update the PC, you need to set the LSB of the new PC value to 1 to indicate the Thumb state. Otherwise, a fault exception can be triggered, as it indicates an attempt to switch to use ARM instructions (i.e., 32-bit ARM instructions as in ARM7TDMI), which is not supported. In high-level programming languages (including C, C++), the setting of LSB in branch targets is handled by the compiler automatically. It is less common to use data processing instructions to update the PC. However, the value of PC is useful for accessing literal data stored in program memory. So you can frequently find memory read operations with PC as base address register with address offsets generated by immediate values in the instructions. Special Registers: Besides the registers in the register bank, there are several special registers as shown in figure 4. Figure 4: Special Registers These registers contain the processor status, define the operation states and interrupt/exception masking. In the development of simple applications with high level programming languages such as C, there are not many scenarios that require access to these registers. However, they are needed for development of an embedded OS, or when advanced interrupt masking features are needed. Special registers are not memory mapped, and can be accessed using special register access instructions such as MSR and MRS. MRS , ; Read special register into register MSR , ; write to special register CMSIS-Core also provides several C functions that can be used to access special registers. Program Status Registers: The Program Status Register is composed of three status registers: 1. Application PSR (APSR) 2. Execution PSR (EPSR) 3. Interrupt PSR (IPSR) These three registers shown in figure 5 can be accessed as one combined register, referred to as xPSR in some documentation. In ARM assembler, when accessing xPSR shown in Figure 6, the symbol PSR is used. Figure 5: APSR, IPSR, and EPSR Figure 6: Combined xPSR Below code snippet illustrates the accessing of all the three registers of PSR MRS r0, PSR; Read the combined program status word MSR PSR, r0; Write combined program state word ... ...

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