Test09_VGA_Test
所属分类：嵌入式/单片机/硬件编程
开发工具：Vivado
文件大小：238KB
下载次数：0
上传日期：2020-07-08 11:34:55
上 传 者：
5648424
说明： 在Vivado上编程的VGA测试工程文件，使用Verilog语言，文件完整
(In Vivado programming VGA test project files, using Verilog language, file integrity)
文件列表:
Test09_VGA_Test (0, 2019-01-08)
Test09_VGA_Test\project_1.cache (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\activehdl (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\ies (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\modelsim (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\questa (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\riviera (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\vcs (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\compile_simlib\xcelium (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2 (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711 (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711.logs (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711.logs\runme.log (20983, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\51ca611ee2c23711.xci (37608, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\pll.dcp (8803, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\pll_sim_netlist.v (5651, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\pll_sim_netlist.vhdl (5459, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\pll_stub.v (1286, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\pll_stub.vhdl (1322, 2019-01-08)
Test09_VGA_Test\project_1.cache\ip\2018.2\51ca611ee2c23711\stats.txt (106, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt (0, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt\gui_handlers.wdf (4416, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt\java_command_handlers.wdf (1606, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt\project.wpc (121, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt\synthesis.wdf (5390, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt\synthesis_details.wdf (100, 2019-01-08)
Test09_VGA_Test\project_1.cache\wt\webtalk_pa.xml (4889, 2019-01-08)
Test09_VGA_Test\project_1.hw (0, 2019-01-08)
Test09_VGA_Test\project_1.hw\hw_1 (0, 2019-01-08)
Test09_VGA_Test\project_1.hw\hw_1\hw.xml (1509, 2019-01-08)
Test09_VGA_Test\project_1.hw\hw_1\layout (0, 2019-01-08)
Test09_VGA_Test\project_1.hw\hw_1\wave (0, 2019-01-08)
Test09_VGA_Test\project_1.hw\project_1.lpr (343, 2019-01-08)
Test09_VGA_Test\project_1.ip_user_files (0, 2019-01-08)
Test09_VGA_Test\project_1.ip_user_files\ip (0, 2019-01-08)
Test09_VGA_Test\project_1.ip_user_files\ipstatic (0, 2019-01-08)
Test09_VGA_Test\project_1.ip_user_files\ipstatic\mmcm_pll_drp_func_7s_mmcm.vh (24240, 2019-01-08)
Test09_VGA_Test\project_1.ip_user_files\ipstatic\mmcm_pll_drp_func_7s_pll.vh (19041, 2019-01-08)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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