说明：  集成电路设计越来越向系统级的方向发展, 并且越来越强调模块化的设计。SP I (Serial PeripheralBus) 总线 是M o to ro la 公司提出的一个同步串行外设接口, 容许 CPU 与各种外围接口器件以串行方式进行通信、交换信息。本文简 述了 SP I 总线的特点, 介绍了其 4 条信号线, SP I 串行总线接口的典型应用。重点描述了 SP I 串行总线接口在一款 802111b 芯片中的位置, 及该接口作为基带和射频的通讯接口所完成的功能, 并给出了用硬件描述语言 V erilog HDL 实现该接口的 部分程序。该实现已经在M odelsim 中完成了仿真, 并经过了 FPGA 验证, 最后给出了仿真和验证的结果。
(Integrated circuit design is more and more system level, and more emphasis on modular design. SPI (serial peripheral bus) bus is a synchronous serial peripheral interface proposed by Mo to Rola company, which allows CPU to communicate and exchange information with various peripheral interface devices in serial mode. This paper briefly describes the characteristics of SPI bus, introduces its four signal lines and typical application of SPI serial bus interface. This paper mainly describes the position of SPI serial bus interface in a 802111b chip, and the functions of the interface as the communication interface between baseband and and RF. It also gives part of the program to realize the interface with the Hardware Description Language Verilog HDL. The implementation has been simulated in Modelsim and verified by FPGA. Finally, the simulation and verification results are given.)