FPGA_OV5640_VGA_DDR3_code
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：9315KB
下载次数：5
上传日期：2020-07-15 21:24:33
上 传 者：
严先生啊
说明： 基于OV5640摄像头的视频图像传输存储以及读取。供大家参考。
(Video image transmission, storage and reading based on ov5640 camera. For your reference.)
文件列表:
FPGA_OV5640_VGA_DDR3_code\doc\数据手册\ADV7123.pdf (298797, 2018-08-30)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册\OV5640_datasheet.pdf (2272692, 2018-08-29)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册\OV5640_自动对焦照相模组应用指南(DVP_接口)__R2.13C.pdf (2154136, 2018-08-29)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册\video display information format.pdf (1073567, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册解读\compression mode 3 timing.PNG (41924, 2018-09-12)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册解读\DVP timing.PNG (108810, 2018-08-31)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册解读\ov5640 datasheet阅读.txt (1986, 2018-08-30)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册解读\power on timing.PNG (114864, 2018-09-12)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册解读\SCCB Slave ID.PNG (92396, 2018-08-24)
FPGA_OV5640_VGA_DDR3_code\doc\数据手册解读\SCCB timing.PNG (63903, 2018-09-12)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\chipscope\ov5640_vga_test.cdc (5261, 2018-09-07)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ddr3_wr_ctr.cmd_log (620, 2018-08-31)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ddr3_wr_ctr.lso (6, 2018-09-06)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ddr3_wr_ctr.prj (845, 2018-09-06)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ddr3_wr_ctr.stx (6130, 2018-09-06)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ddr3_wr_ctr.tfi (1285, 2018-08-31)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ddr3_wr_ctr.xst (1214, 2018-09-06)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\iic_commu.lso (6, 2018-09-11)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\iic_commu.prj (38, 2018-09-11)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\iic_commu.stx (1799, 2018-09-11)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\iic_commu.xst (1210, 2018-09-11)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\coregen.cgp (238, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\coregen.log (5603, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\create_ddr3_mig.tcl (1273, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\docs\ug388.pdf (2172724, 2013-10-14)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\docs\ug416.pdf (80254, 2013-10-14)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\datasheet.txt (2452, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\log.txt (3333, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\mig.prj (3169, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\create_ise.bat (3143, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\example_top.ucf (10875, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\icon_coregen.xco (1382, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\ila_coregen.xco (3871, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\ise_flow.bat (3931, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\ise_run.txt (1279, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\makeproj.bat (28, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\mem_interface_top.ut (385, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\rem_files.bat (7952, 2018-09-03)
FPGA_OV5640_VGA_DDR3_code\proj\ov5640_vga_ctr\ipcore_dir\ddr3_mig\ddr3_mig\example_design\par\set_ise_prop.tcl (5877, 2018-09-03)
... ...
The following files were generated for 'icon_pro' in directory
E:\Others\Alinx\XC6SLX16\FPGA_CODE\ov5***0_vga_demo\proj\ov5***0_vga_ctr\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：