verilog_curr_design
所属分类：VHDL/FPGA/Verilog
开发工具：Quartus II
文件大小：954KB
下载次数：1
上传日期：2020-07-16 21:49:36
上 传 者：
wtq0
说明： 实现中采用 Verilog HDL 描述、 ModelSim 进行功能仿真、 Quartus II 进行逻辑综合和适配下载
(Design of table tennis game machine)
文件列表:
verilog_curr_design (0, 2017-05-11)
verilog_curr_design\1k_f.v (2197, 2017-04-12)
verilog_curr_design\1k_f.v.bak (2197, 2017-04-12)
verilog_curr_design\db (0, 2017-05-11)
verilog_curr_design\db\logic_util_heursitic.dat (15048, 2017-04-18)
verilog_curr_design\db\pingpong.(0).cnf.cdb (1458, 2017-04-16)
verilog_curr_design\db\pingpong.(0).cnf.hdb (1083, 2017-04-16)
verilog_curr_design\db\pingpong.(1).cnf.cdb (24153, 2017-04-16)
verilog_curr_design\db\pingpong.(1).cnf.hdb (3017, 2017-04-16)
verilog_curr_design\db\pingpong.(2).cnf.cdb (2102, 2017-04-12)
verilog_curr_design\db\pingpong.(2).cnf.hdb (853, 2017-04-12)
verilog_curr_design\db\pingpong.amm.cdb (299, 2017-04-18)
verilog_curr_design\db\pingpong.asm.qmsg (2228, 2017-04-18)
verilog_curr_design\db\pingpong.asm.rdb (1453, 2017-04-18)
verilog_curr_design\db\pingpong.asm_labs.ddb (8485, 2017-04-18)
verilog_curr_design\db\pingpong.atom_map.rvd (28939, 2017-04-16)
verilog_curr_design\db\pingpong.cbx.xml (90, 2017-04-18)
verilog_curr_design\db\pingpong.cmp.bpm (914, 2017-04-18)
verilog_curr_design\db\pingpong.cmp.cdb (48473, 2017-04-18)
verilog_curr_design\db\pingpong.cmp.hdb (15652, 2017-04-18)
verilog_curr_design\db\pingpong.cmp.kpt (214, 2017-04-18)
verilog_curr_design\db\pingpong.cmp.logdb (4, 2017-04-18)
verilog_curr_design\db\pingpong.cmp.rdb (16475, 2017-04-18)
verilog_curr_design\db\pingpong.cmp0.ddb (166436, 2017-04-18)
verilog_curr_design\db\pingpong.cmp1.ddb (163347, 2017-04-18)
verilog_curr_design\db\pingpong.cmp2.ddb (55395, 2017-04-18)
verilog_curr_design\db\pingpong.cmp_merge.kpt (218, 2017-04-18)
verilog_curr_design\db\pingpong.db_info (152, 2017-04-12)
verilog_curr_design\db\pingpong.fit.qmsg (29072, 2017-04-18)
verilog_curr_design\db\pingpong.hier_info (4690, 2017-04-18)
verilog_curr_design\db\pingpong.hif (1649, 2017-04-18)
verilog_curr_design\db\pingpong.idb.cdb (6281, 2017-04-18)
verilog_curr_design\db\pingpong.lpc.html (1196, 2017-04-18)
verilog_curr_design\db\pingpong.lpc.rdb (467, 2017-04-18)
verilog_curr_design\db\pingpong.lpc.txt (1696, 2017-04-18)
verilog_curr_design\db\pingpong.map.bpm (882, 2017-04-18)
verilog_curr_design\db\pingpong.map.cdb (14272, 2017-04-18)
verilog_curr_design\db\pingpong.map.hdb (14954, 2017-04-18)
verilog_curr_design\db\pingpong.map.kpt (2139, 2017-04-18)
verilog_curr_design\db\pingpong.map.logdb (4, 2017-04-18)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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