rfid-verilog-master
所属分类：其他
开发工具：Verilog
文件大小：54KB
下载次数：3
上传日期：2020-07-23 15:32:51
上 传 者：
woodboy
说明： RFID 中主机模块的verilog语言实现
(The moule of RFID in verilog)
文件列表:
reader (0, 2013-04-05)
reader\rfid_reader.v (6936, 2013-04-05)
reader\rfid_reader_map.v (161071, 2013-04-05)
reader\rfid_reader_packet_rxtx.v (11920, 2013-04-05)
reader\rfid_reader_rx.v (3937, 2013-04-05)
reader\rfid_reader_tx.v (4996, 2013-04-05)
tag (0, 2013-04-05)
tag\cmdparser.v (3544, 2013-04-05)
tag\controller.v (9308, 2013-04-05)
tag\counter10.v (518, 2013-04-05)
tag\crc16.v (2274, 2013-04-05)
tag\divby2.v (360, 2013-04-05)
tag\epc.v (914, 2013-04-05)
tag\packetparse.v (9723, 2013-04-05)
tag\preamble.v (2410, 2013-04-05)
tag\read.v (1669, 2013-04-05)
tag\rng.v (1925, 2013-04-05)
tag\rx.v (3605, 2013-04-05)
tag\sequencer.v (3649, 2013-04-05)
tag\sevenseg.v (1321, 2013-04-05)
tag\top.v (7447, 2013-04-05)
tag\toptest.v (3402, 2013-04-05)
tag\tx.v (6327, 2013-04-05)
tag\txclkdivide.v (1518, 2013-04-05)
tag\txsettings.v (893, 2013-04-05)
tag\uid.v (1623, 2013-04-05)
Copyright 2010 University of Washington
License: http://creativecommons.org/licenses/by/3.0/
Original author: Dan Yeager, University of Washington
This code is split into two separate branches:
- master: every READ command causes a sample.
- fifo: the ADC interface has a FIFO.
TODO: merge master and fifo branches and use Verilog `ifdef <...> `endif to
select between versions at compile time.
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