bnn-fpga-master
所属分类：VHDL/FPGA/Verilog
开发工具：C++
文件大小：318KB
下载次数：5
上传日期：2020-07-27 07:02:34
上 传 者：
dosproject
说明： bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。
(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)
文件列表:
LICENSE (1501, 2018-01-25)
cpp (0, 2018-01-25)
cpp\Makefile (161, 2018-01-25)
cpp\Makefile.inc (109, 2018-01-25)
cpp\accel (0, 2018-01-25)
cpp\accel\Accel.cpp (29353, 2018-01-25)
cpp\accel\Accel.h (4014, 2018-01-25)
cpp\accel\AccelPrint.cpp (905, 2018-01-25)
cpp\accel\AccelPrint.h (2145, 2018-01-25)
cpp\accel\AccelSchedule.cpp (10101, 2018-01-25)
cpp\accel\AccelSchedule.h (1737, 2018-01-25)
cpp\accel\AccelTest.cpp (9437, 2018-01-25)
cpp\accel\AccelTest.h (3497, 2018-01-25)
cpp\accel\Dense.cpp (2521, 2018-01-25)
cpp\accel\Dense.h (449, 2018-01-25)
cpp\accel\InputConv.cpp (2317, 2018-01-25)
cpp\accel\InputConv.h (296, 2018-01-25)
cpp\accel\Makefile (706, 2018-01-25)
cpp\accel\accel_test_bnn.cpp (5817, 2018-01-25)
cpp\accel\accel_test_layer.cpp (3276, 2018-01-25)
cpp\accel\accel_test_random.cpp (2553, 2018-01-25)
cpp\accel\hls.tcl (1040, 2018-01-25)
cpp\accel\opt.tcl (3772, 2018-01-25)
cpp\accel\parse_vivado.py (8152, 2018-01-25)
cpp\accel\sdsoc_build (0, 2018-01-25)
cpp\accel\sdsoc_build\Makefile (1016, 2018-01-25)
cpp\accel\sdsoc_build\libhf_minizip (0, 2018-01-25)
cpp\accel\sdsoc_build\libhf_minizip\libaes.a (60870, 2018-01-25)
cpp\accel\sdsoc_build\libhf_minizip\libminizip.a (55634, 2018-01-25)
cpp\accel\sdsoc_build\libhf_minizip\libz.a (91814, 2018-01-25)
cpp\accel\sdsoc_build\sds.tcl (461, 2018-01-25)
cpp\minizip (0, 2018-01-25)
cpp\minizip\CMakeLists.txt (2881, 2018-01-25)
cpp\minizip\ChangeLog (4975, 2018-01-25)
cpp\minizip\LICENSE (876, 2018-01-25)
cpp\minizip\Makefile (1109, 2018-01-25)
... ...
Publications
------------------------------------------------------------------------
If you use this code in your research, please cite our [FPGA'17 paper][1]:
```
@article{zhao-bnn-fpga2017,
title = "{Accelerating Binarized Convolutional Neural Networks
with Software-Programmable FPGAs}",
author = {Ritchie Zhao and Weinan Song and Wentao Zhang and Tianwei Xing and
Jeng-Hau Lin and Mani Srivastava and Rajesh Gupta and Zhiru Zhang},
journal = {Int'l Symp. on Field-Programmable Gate Arrays (FPGA)},
month = {Feb},
year = {2017},
}
```
[1]: http://dx.doi.org/10.1145/3020078.3021741
Introduction
------------------------------------------------------------------------
bnn-fpga is an open-source implementation of a binarized neural network (BNN)
accelerator for CIFAR-10 on FPGA.
The architecture and training of the BNN is proposed by [Courbarieaux et al.][2]
and open-source Python code is available at https://github.com/MatthieuCourbariaux/BinaryNet.
Our accelerator targets low-power embedded field-programmable SoCs and was
tested on a Zedboard. At time of writing the error rate on the 10000 images
in the CIFAR-10 test set is **11.19%**.
[2]: https://arxiv.org/abs/1602.02830
Build Setup
------------------------------------------------------------------------
You will need Xilinx SDSoC on your PATH and the Vivado HLS
header include files on your CPATH.
Verified SDSoC versions: 201***, 2017.1
With these tools in place do the following from the repository root:
```
% source setup.sh
% cd data; ./get_data.sh; cd ..
% cd params; ./get_params.sh; cd ..
```
This will set environment variables and download data and parameter zip files.
To build the software model:
```
% cd cpp
% make -j4
```
To build the FPGA bitstream do (with the software build complete):
```
% cd cpp/accel/sdsoc_build
% make -j4
```
Post-route timing and area information is available in
**sdsoc_build/\_sds/reports/sds.rpt**.
Branches
------------------------------------------------------------------------
The master branch contains a debug build including a random testbench,
a per-layer testbench, and a full bnn testbench. The optimized branch
contains only the full testbench.
FPGA Evaluation
------------------------------------------------------------------------
1. After the FPGA bitstream is finished building, copy the **sd_card**
directory onto an SD card.
2. Copy both **data** and **params** directories onto the same SD card.
3. Insert the card into the Zedboard and power on the Zedboard.
4. Connect to the Zedboard via USB and wait for the boot sequence to finish.
5. At the terminal prompt do the following:
```
% cd mnt
% export CRAFT_BNN_ROOT=.
% ./accel_test_bnn.exe
```
Where N is the number of images you want to test. Up to 10000 images from
the CIFAR-10 test set are available. The program will print out the
prediction accuracy and accelerator runtime at the end. Note that the
program performs weight binarization and reordering before invoking
the accelerator so there will be a pause at the very beginning.
Varying the Number of Convolvers
------------------------------------------------------------------------
Go to **cpp/accel/Accel.h** and change CONVOLVERS to the desired number
(must be a power of 2). You must do a make clean and rebuild everything
from scratch.
Known Issues and Bugs
------------------------------------------------------------------------
1. SDSoC compilation error due to glibc include file (Issue #1) \
This occurs if SDSoC sees the native version of glibc on CPATH, overriding the ARM version for cross-compilation. The fix is to remove /usr/include from CPATH. In some cases this prevents SDSoC from seeing zlib; currently the suggested fix is to build zlib in a different (non-system) directory and add that to CPATH.
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