DDS_50M
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：13009KB
下载次数：2
上传日期：2020-07-31 13:46:45
上 传 者：
5765678
说明： 打包好的ISE工程，可以直接使用，通过ISE内部调用的IP核产生输出正弦信号。
(The packaged ISE project, which can be used directly, generates output sinusoidal signals through the IP core invoked internally by ISE.)
文件列表:
DDS_50M (0, 2020-07-27)
DDS_50M\chipscope.cdc (2705, 2016-04-16)
DDS_50M\DDS.gise (17172, 2020-07-27)
DDS_50M\DDS.xise (43818, 2020-07-23)
DDS_50M\DDS_CORE.v (811, 2020-07-22)
DDS_50M\DDS_CORE_summary.html (3700, 2016-04-16)
DDS_50M\dds_top.bgn (7350, 2020-07-23)
DDS_50M\dds_top.bit (464586, 2020-07-23)
DDS_50M\dds_top.bld (1099, 2020-07-23)
DDS_50M\dds_top.cmd_log (40227, 2020-07-23)
DDS_50M\dds_top.drc (559, 2020-07-23)
DDS_50M\dds_top.fdo (1310, 2016-11-21)
DDS_50M\dds_top.lso (6, 2020-07-23)
DDS_50M\dds_top.ncd (74702, 2020-07-23)
DDS_50M\dds_top.ngc (20145, 2020-07-23)
DDS_50M\dds_top.ngd (190872, 2020-07-23)
DDS_50M\dds_top.ngr (14777, 2020-07-23)
DDS_50M\dds_top.pad (13545, 2020-07-23)
DDS_50M\dds_top.par (8294, 2020-07-23)
DDS_50M\dds_top.pcf (13897, 2020-07-23)
DDS_50M\dds_top.prj (86, 2020-07-23)
DDS_50M\dds_top.ptwx (17234, 2020-07-23)
DDS_50M\dds_top.stx (0, 2020-07-23)
DDS_50M\dds_top.syr (18724, 2020-07-23)
DDS_50M\dds_top.twr (6418, 2020-07-23)
DDS_50M\dds_top.twx (25327, 2020-07-23)
DDS_50M\dds_top.ucf (4907, 2020-07-23)
DDS_50M\dds_top.udo (384, 2016-11-21)
DDS_50M\dds_top.unroutes (157, 2020-07-23)
DDS_50M\dds_top.ut (553, 2020-07-23)
DDS_50M\dds_top.v (2111, 2020-07-23)
DDS_50M\dds_top.xpi (46, 2020-07-23)
DDS_50M\dds_top.xst (1093, 2020-07-23)
DDS_50M\dds_top_bitgen.xwbt (281, 2020-07-23)
DDS_50M\dds_top_cs.blc (836, 2016-04-16)
DDS_50M\dds_top_cs.ngc (80807, 2016-04-16)
DDS_50M\dds_top_envsettings.html (18972, 2020-07-27)
DDS_50M\dds_top_guide.ncd (74702, 2020-07-23)
DDS_50M\dds_top_map.map (8158, 2020-07-23)
DDS_50M\dds_top_map.mrp (23044, 2020-07-23)
... ...
The following files were generated for 'DDS' in directory
C:\Users\Administrator\Desktop\sin\dds1\DDS_10M\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* DDS.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* DDS.ngc
Obfuscate Netlist Generator:
Please see the core data sheet.
* DDS.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* DDS.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* DDS.v
All Documents Generator:
Please see the core data sheet.
* DDS/doc/dds_compiler_v4_0_vinfo.html
* DDS/doc/dds_ds558.pdf
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* DDS.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* DDS.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* DDS_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* DDS.gise
* DDS.xise
* _xmsgs/pn_parser.xmsgs
Deliver Readme:
Readme file for the IP.
* DDS_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* DDS_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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